IT8502F View Datasheet(PDF) - ITE Tech. INC.
Part Name
Description
Manufacturer
IT8502F Datasheet PDF : 398 Pages
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Contents
6.2.10.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ........................... 61
6.2.10.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ....................... 61
6.2.10.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ........................... 61
6.2.10.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX) .................. 62
6.2.10.7 Interrupt Request Type Select (IRQTP)................................................................ 62
6.2.11 Power Management I/F Channel 2 Configuration Registers.............................................. 63
6.2.11.1 Logical Device Activate Register (LDA)................................................................ 63
6.2.11.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ....................... 63
6.2.11.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ........................... 63
6.2.11.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ....................... 63
6.2.11.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ........................... 63
6.2.11.6 I/O Port Base Address Bits [15:8] for Descriptor 2 (IOBAD2[15:8]) ....................... 64
6.2.11.7 I/O Port Base Address Bits [7:0] for Descriptor 2 (IOBAD2[7:0]) ........................... 64
6.2.11.8 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX) .................. 64
6.2.11.9 Interrupt Request Type Select (IRQTP)................................................................ 64
6.2.11.10 General Purpose Interrupt (GPINTR) ................................................................... 64
6.2.12 Power Management I/F Channel 3 Configuration Registers.............................................. 64
6.2.12.1 Logical Device Activate Register (LDA)................................................................ 65
6.2.12.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ....................... 65
6.2.12.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ........................... 65
6.2.12.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ....................... 65
6.2.12.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ........................... 65
6.2.12.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX) .................. 65
6.2.12.7 Interrupt Request Type Select (IRQTP)................................................................ 66
6.2.13 Serial Peripheral Interface (SSPI) Configuration Registers ............................................... 67
6.2.13.1 Logical Device Activate Register (LDA)................................................................ 67
6.2.13.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ....................... 67
6.2.13.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ........................... 67
6.2.13.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ....................... 67
6.2.13.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ........................... 67
6.2.13.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX) .................. 68
6.2.13.7 Interrupt Request Type Select (IRQTP)................................................................ 68
6.2.14 Programming Guide......................................................................................................... 69
6.3 Shared Memory Flash Interface Bridge (SMFI)............................................................................. 71
6.3.1 Overview ......................................................................................................................... 71
6.3.2 Features .......................................................................................................................... 71
6.3.3 Function Description ........................................................................................................ 71
6.3.3.1 Supported Interface ............................................................................................. 71
6.3.3.2 Supported Flash .................................................................................................. 71
6.3.3.3 HLPC: Host Translation ....................................................................................... 71
6.3.3.4 HLPC: Memory Mapping...................................................................................... 71
6.3.3.5 HLPC: Host-Indirect Memory Read/Write Transaction .......................................... 72
6.3.3.6 EC-Indirect Memory Read/Write Transaction ....................................................... 72
6.3.3.7 Flash Shared between Host and EC Domains...................................................... 72
6.3.3.8 Host Access Protection........................................................................................ 73
6.3.3.9 Serial Flash Performance Consideration .............................................................. 73
6.3.3.10 Response to a Forbidden Access......................................................................... 73
6.3.3.11 Scratch SRAM ..................................................................................................... 73
6.3.3.12 DMA for Scratch SRAM ....................................................................................... 74
6.3.3.13 HLPC: Flash Programming via Host LPC Interface with Scratch SRAM................ 75
6.3.3.14 Force 8032 to Code Fetch from Internal SRAM .................................................... 75
6.3.3.15 Force 8032 to Clear Dynamic Caches.................................................................. 75
6.3.3.16 HLPC: Serial Flash Programming ........................................................................ 76
6.3.3.17 Host Side to EC Scratch RAM (H2RAM) .............................................................. 76
6.3.3.17.1 HLPC to EC Scratch RAM (H2RAM-HLPC) ................................... 76
6.3.3.18 SPI Flash Power-on Detection ............................................................................. 77
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