HT46R47 View Datasheet(PDF) - Unspecified
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HT46R47 Datasheet PDF : 45 Pages
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HT46R47
sired control sequence, the contents should be
saved in advance.
External interrupts are triggered by a high to
low transition of INT and the related interrupt
request flag (EIF; bit 4 of INTC) will be set.
When the interrupt is enabled, the stack is not
full and the external interrupt is active, a sub-
routine call to location 04H will occur. The in-
terrupt request flag (EIF) and EMI bits will be
cleared to disable other interrupts.
The internal timer/event counter interrupt is
initialized by setting the timer/event counter
interrupt request flag (TF; bit 5 of INTC),
caused by a timer overflow. When the interrupt
is enabled, the stack is not full and the TF bit is
set, a subroutine call to location 08H will occur.
The related interrupt request flag (TF) will be
reset and the EMI bit cleared to disable further
interrupts.
The A/D converter interrupt is initialized by
setting the A/D converter request flag (ADF; bit
6 of INTC), caused by an end of A/D conversion.
When the interrupt is enabled, the stack is not
full and the ADF is set, a subroutine call to loca-
tion 0CH will occur. The related interrupt re-
quest flag (ADF) will be reset and the EMI bit
cleared to disable further interrupts.
During the execution of an interrupt subroutine,
other interrupt acknowledgments are held until
the "RETI" instruction is executed or the EMI
bit and the related interrupt control bit are set to
1 (of course, if the stack is not full). To return
from the interrupt subroutine, "RET" or "RETI"
may be invoked. RETI will set the EMI bit to en-
able an interrupt service, but RET will not.
Interrupts, occurring in the interval between
the rising edges of two consecutive T2 pulses,
will be serviced on the latter of the two T2
pulses, if the corresponding interrupts are en-
abled. In the case of simultaneous requests the
following table shows the priority that is ap-
plied. These can be masked by resetting the
EMI bit.
No. Interrupt Source Priority Vector
a External Interrupt
1
04H
b
Timer/event
Counter Overflow
2
08H
c
A/D Converter
Interrupt
3
0CH
The timer/event counter interrupt request flag
(TF), external interrupt request flag (EIF), A/D
Register Bit No. Label
Function
0
EMI
Controls the master (global) interrupt
(1= enabled; 0= disabled)
1
EEI
Controls the external interrupt
(1= enabled; 0= disabled)
2
ETI
Controls the timer/event counter interrupt
(1= enabled; 0= disabled)
INTC
3
EADI
Controls the A/D converter interrupt
(1= enabled; 0= disabled)
(0BH)
4
EIF
External interrupt request flag
(1= active; 0= inactive)
5
TF
Internal timer/event counter request flag
(1= active; 0= inactive)
6
ADF
A/D converter request flag
(1= active; 0= inactive)
7
¾
Unused bit, read as "0"
INTC register
Rev. 1.40
11
July 18, 2001
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