IDTCV119E View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
Manufacturer
IDTCV119E Datasheet PDF : 21 Pages
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IDTCV119E
CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
COMMERCIAL TEMPERATURE RANGE
PD# DE-ASSERTION
The time from the de-assertion of PD# or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive mode control bit for PD# tristate
is programmed to ‘1’ the stopped differential pair must first be driven high to a minimum of 200mV in less than 300µs of PD# deassertion.
PWRDWN#
tSTABLE <1.8mS
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818
tDRIVE_PWRDWN#
<300µS, <200mV
N PROGRAMMING JITTER MEASUREMENT
Tested on IDT test board, 10" trace, 10pF loading.
Measured at CPU0, differential active probe.
Data showed may vary due to CMOS process.
100MHz MODE
N=
Output Freq. (MHz)
200h (512)
115
300h (768)
172
3FFh (1023)
229
CPU Jitter (ps)
80
51
65
133MHz MODE
N=
Output Freq. (MHz)
200h (512)
153
300h (768)
229
3FFh (1023)
306
CPU Jitter (ps)
76
79
72
166MHz MODE
N=
Output Freq. (MHz)
200h (512)
204
300h (768)
305
3FFh (1023)
407
CPU Jitter (ps)
71
72
92
200MHz MODE
N=
Output Freq. (MHz)
200h (512)
229
300h (768)
344
3FFh (1023)
458
20
CPU Jitter (ps)
68
84
82
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