TLK3138 View Datasheet(PDF) - Unspecified
Part Name
Description
Manufacturer
TLK3138 Datasheet PDF : 61 Pages
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TLK3138
SLLS762A – FEBRUARY 2007 – REVISED APRIL 2007
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION
The TLK3138 is an eight channel serial transceiver. It is compliant with the 10Gbps Ethernet XAUI specification.
The TLK3138 provides 10 Gbps high-speed bi-directional point-to-point data transmission. The primary
application of this device is in backplanes and front panel connections requiring dual/redundant 10Gbps
connections over controlled impedance media of approximately 50Ω. The transmission media can be printed
circuit board (PCB) traces, copper cables or fiber-optical media. The ultimate rate and distance of data transfer
is dependent upon the attenuation characteristics of the media and the noise coupling into the lines.
The TLK3138 performs the parallel-to-serial, serial-to-parallel conversion, and clock extraction functions for a
physical layer interface. The TLK3138 provides two complete XGXS/PCS functions defined in Clause 47/48 of
the IEEE P802.3ae 10Gbps Ethernet standard. The serial transmitter is implemented using differential Current
Mode Logic (CML) with integrated termination resistors.
The TLK3138 can be configured as a dual XAUI transceiver. TLK3138 supports two 32-bit data path, 4-bit
control, 10 Gigabit Media Independent Interfaces (XGMII) to the protocol device(s). Figure 1 shows an example
system block diagram for TLK3138 used to provide the 10Gbps Ethernet Physical Coding Sublayer to Coarse
Wave-length Division Multiplexed optical transceiver or parallel optics.
Line Card
TX
4
CH A
A
4
XAUI
TLK3138
RX
A
MAC/
Packet
Processor
TCLK
TD(31:0)
TC(3:0)
4
CH A
4
XAUI
TLK3138
RC(3:0)
RCLK
RD(31:0)
4
CH B
4
XAUI
CWDM
or
Parallel
Optics
CWDM
or
Parallel
Optics
TX
B
4
CH B
4
XAUI
RX
B
MAC/
Packet
Processor
TCLK
TD(31:0)
TC(3:0)
RC(3:0)
RCLK
RD(31:0)
Figure 1. System Block Diagram – PCS
2
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