NT68665 View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

NT68665

Flat Panel Monitor Controller

Unspecified 

Extract Vsync from Composite/SOG Signal

Vsync

Hsync

ORed

XORed

Single

Serrated

NT68665/NT68625

Double

Serrated + Equal.

Extracted VSO

Internal Coast

Extracted HSO from

SOGI / HSYNCI

Internal Coast

Extracted HSO from

SOG / HSYNCI

Pre-Equal. Pulses

Serration Pulses

Post-Equal. Pulses

Vertical Blanking Interval

textract(VSO) = fixed

PRE_COAST = 3

tPW(insert)

tw iden(VSO)

POS_COAST = 3

Inserted Pulses

tPW(insert)

Inserted Pulses

H/V Sync Timing

Figure 6.8-1 H/V Timing

Internal Odd/Even Field Detection

Included in the sync detector is circuitry to determine which field is currently being input for interlaced

input. To determine the field based on position of VSYNC relative to HSYNC, the GI_FLD_WINBEG

(3:0) and GI_FLD_WINEND (3:0) registers are used for Graphic Port and the VI_FLD_WINBEG (3:0)

and VI_FLD_WINEND (3:0) registers are used for Video Port. The NT68665/NT68625 divides each

horizontal line into 16 equal intervals. The FLD_WINBEG bits are used to specify at which 1/16th of a

line to start looking for the leading edge of VSYNC. The FLD_WINEND bits are used to specify at

which 1/16th of a line to stop looking. If the leading edge of VSYNC occurs between during or after the

1/16th line specified by FLD_WINBEG, but no later than the 1/16th line specified by FLD_WINEND, the

current field is marked as odd. Otherwise, a leading edge transition outside these boundaries will

cause the current field to be marked even.

2006-02-09

26

Ver. 0.40

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