R5F7131 View Datasheet(PDF) - Renesas Electronics
Part Name
Description
Manufacturer
R5F7131 Datasheet PDF : 1184 Pages
| |||
16.8.5 Reading ICDRR in Master Receive Mode............................................................ 682
16.8.6 Supported Emulator .............................................................................................. 682
Section 17 A/D Converter (ADC) .....................................................................683
17.1 Features.............................................................................................................................. 683
17.2 Input/Output Pins............................................................................................................... 686
17.3 Register Descriptions ......................................................................................................... 687
17.3.1 A/D Control Registers_0 and _1 (ADCR_0 and ADCR_1) ................................. 688
17.3.2 A/D Status Registers_0 and _1 (ADSR_0 and ADSR_1)..................................... 691
17.3.3 A/D Start Trigger Select Registers_0 and _1
(ADSTRGR_0 and ADSTRGR_1)....................................................................... 692
17.3.4 A/D Analog Input Channel Select Registers_0 and _1
(ADANSR_0 and ADANSR_1) ........................................................................... 694
17.3.5 A/D Data Registers 0 to 15 (ADDR0 to ADDR15) .............................................. 695
17.3.6 CPU Interface ....................................................................................................... 696
17.4 Operation ........................................................................................................................... 697
17.4.1 Single-Cycle Scan Mode ...................................................................................... 697
17.4.2 Continuous Scan Mode......................................................................................... 699
17.4.3 Input Sampling and A/D Conversion Time .......................................................... 701
17.4.4 A/D Converter Activation by MTU2 and MTU2S ............................................... 703
17.4.5 External Trigger Input Timing.............................................................................. 704
17.4.6 Example of ADDR Auto-Clear Function.............................................................. 704
17.5 Interrupt Sources and DTC Transfer Requests .................................................................. 706
17.6 Definitions of A/D Conversion Accuracy.......................................................................... 707
17.7 Usage Notes ....................................................................................................................... 709
17.7.1 Analog Input Voltage Range ................................................................................ 709
17.7.2 Relationship between AVcc, AVss and Vcc, Vss................................................. 709
17.7.3 Range of AVrefh and AVrefl Pin Settings.................................................................. 709
17.7.4 Notes on Board Design ......................................................................................... 709
17.7.5 Notes on Noise Countermeasures ......................................................................... 710
17.7.6 Notes on Register Setting ..................................................................................... 710
Section 18 Compare Match Timer (CMT) ........................................................711
18.1 Features.............................................................................................................................. 711
18.2 Register Descriptions ......................................................................................................... 712
18.2.1 Compare Match Timer Start Register (CMSTR) .................................................. 713
18.2.2 Compare Match Timer Control/Status Register (CMCSR) .................................. 713
18.2.3 Compare Match Counter (CMCNT) ..................................................................... 715
18.2.4 Compare Match Constant Register (CMCOR) ..................................................... 715
18.3 Operation ........................................................................................................................... 716
Rev. 3.00 Jan. 18, 2010 Page xviii of xxiv
REJ09B0402-0300
Share Link: 