M1AGL1000V2-FG144I View Datasheet(PDF) - Microsemi Corporation

Part Name

Description

Manufacturer

M1AGL1000V2-FG144I

IGLOO Low Power Flash FPGAs with Flash* Freeze Technology

Microsemi Corporation 

IGLOO Low Power Flash FPGAs

with Flash*Freeze Technology

Revision 23

Features and Benefits

Low Power

• 1.2 V to 1.5 V Core Voltage Support for Low Power

• Supports Single-Voltage System Operation

• 5 µW Power Consumption in Flash*Freeze Mode

• Low Power Active FPGA Operation

• Flash*Freeze Technology Enables Ultra-Low Power

Consumption while Maintaining FPGA Content

• Easy Entry to / Exit from Ultra-Low Power Flash*Freeze Mode

High Capacity

• 15K to 1 Million System Gates

• Up to 144 Kbits of True Dual-Port SRAM

• Up to 300 User I/Os

Reprogrammable Flash Technology

• 130-nm, 7-Layer Metal, Flash-Based CMOS Process

• Instant On Level 0 Support

• Single-Chip Solution

• Retains Programmed Design When Powered Off

• 250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System

Performance

In-System Programming (ISP) and Security

• ISP Using On-Chip 128-Bit Advanced Encryption Standard

(AES) Decryption (except ARM®-enabled IGLOO® devices) via

• FJTlaAsGhL(oIEcEk®ED1e5s3i2g–nceodmtoplSiaenct)u†re FPGA Contents

High-Performance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure

Advanced I/O

• 700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above)

• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—up to 4 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS

3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X†,

and LVCMOS 2.5 V / 5.0 V Input†

• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-

LVDS (AGL250 and above)

• Wide Range Power Supply Voltage Support per JESD8-B,

Allowing I/Os to Operate from 2.7 V to 3.6 V

• Wide Range Power Supply Voltage Support per JESD8-12,

Allowing I/Os to Operate from 1.14 V to 1.575 V

• I/O Registers on Input, Output, and Enable Paths

•

•

HProotg-SrawmamppaabbleleOauntdpuCtoSldle-SwpRarainteg†I/aOnsd‡Drive Strength

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the IGLOO Family

Clock Conditioning Circuit (CCC) and PLL†

• Six CCC Blocks, One with an Integrated PLL

• Configurable Phase Shift, Multiply/Divide, Delay Capabilities,

and External Feedback

• Wide Input Frequency Range (1.5 MHz up to 250 MHz)

Embedded Memory

• 1 kbit of FlashROM User Nonvolatile Memory

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit† RAM

•

Blocks (×1, ×2,

True Dual-Port

S×R4,A×M9,(eaxncde×p1t 8×1o8rg)†anizations)

ARM Processor Support in IGLOO FPGAs

• M1 IGLOO Devices—Cortex™-M1 Soft Processor Available

with or without Debug

IGLOO Devices

AGL0151 AGL030 AGL060 AGL125 AGL250

ARM-Enabled IGLOO Devices2

M1AGL250

AGL400

AGL600

AGL1000

M1AGL600 M1AGL1000

System Gates

15,000

30,000

60,000 125,000

250,000

400,000

600,000

1,000,000

Typical Equivalent Macrocells

128

256

512

1,024

2,048

–

–

–

VersaTiles (D-flip-flops)

384

768

1,536 3,072

6,144

9,216

13,824

24,576

Flash*Freeze Mode (typical, µW) 5

5

10

16

24

32

36

53

RAM kbits (1,024 bits)

–

–

18

36

36

54

108

144

4,608-Bit Blocks

–

–

4

8

8

12

24

32

FlashROM Kbits (1,024 bits)

1

1

1

1

1

1

1

1

AES-Protected ISP 2

–

–

Yes

Yes

Yes

Yes

Yes

Yes

Integrated PLL in CCCs 3

–

–

1

1

1

1

1

1

VersaNet Globals 4

6

6

18

18

18

18

18

18

I/O Banks

2

2

2

2

4

4

4

4

Maximum User I/Os

49

81

96

133

143

194

235

300

Package Pins

UC/CS

QFN

VQFP

FBGA

QN68

UC81

CS121 3

CS81

QN48, QN68, QN132

QN132

VQ100

VQ100

FG144 6

CS196 CS81, CS196 5 CS196

CS281

CS281

QN132

VQ100

FG144

QN132 5,6

VQ100

FG144

FG144, FG256, FG144, FG256, FG144, FG256,

FG484

FG484

FG484

Notes:

1. AGL015 is not recommended for new designs

2. AES is not available for ARM-enabled IGLOO devices.

3. AGL060 in CS121 does not support the PLL.

4. Six chip (main) and twelve quadrant global networks are available for AGL060 and above.

5. The M1AGL250 device does not support this package.

6. Device/package support TBD.

7. The IGLOOe datasheet and IGLOOe FPGA Fabric User’s Guide provide information on higher densities and additional features.

† AGL015 and AGL030 devices do not support this feature.

‡ Supported only by AGL015 and AGL030 devices.

December 2012

I

© 2012 Microsemi Corporation

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