DSP56300AD View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

DSP56300AD

Digital audio applications requiring digital audio compression and decompression, sound field processing, acoustic equalization, and other digital audio algorithms.

Motorola => Freescale 

Freescale Semiconductor, Inc.

Signal/Connection Descriptions

Enhanced Serial Audio Interface

Table 1-11 Enhanced Serial Audio Interface Signals (Continued)

Signal

Name

Signal Type

State during

Reset

Signal Description

FSR

PC1

Input or output

GPIO

disconnected

Input, output,

or

disconnected

Frame Sync for Receiver—This is the receiver

frame sync input/output signal. In the asynchronous

mode (SYN=0), the FSR pin operates as the frame

sync input or output used by all the enabled

receivers. In the synchronous mode (SYN=1), it

operates as either the serial flag 1 pin (TEBE=0), or

as the transmitter external buffer enable control

(TEBE=1, RFSD=1).

When this pin is configured as serial flag pin, its

direction is determined by the RFSD bit in the RCCR

register. When configured as the output flag OF1,

this pin will reflect the value of the OF1 bit in the

SAICR register, and the data in the OF1 bit will show

up at the pin synchronized to the frame sync in

normal mode or the slot in network mode. When

configured as the input flag IF1, the data value at the

pin will be stored in the IF1 bit in the SAISR register,

synchronized by the frame sync in normal mode or

the slot in network mode.

Port C 1—When the ESAI is configured as GPIO,

this signal is individually programmable as input,

output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

Frame Sync for Transmitter—This is the

transmitter frame sync input/output signal. For

FST

Input or output

synchronous mode, this signal is the frame sync for

both transmitters and receivers. For asynchronous

mode, FST is the frame sync for the transmitters

only. The direction is determined by the transmitter

frame sync direction (TFSD) bit in the ESAI transmit

GPIO

clock control register (TCCR).

disconnected

Port C 4—When the ESAI is configured as GPIO,

Input, output,

PC4

or

disconnected

this signal is individually programmable as input,

output, or internally disconnected.

The default state after reset is GPIO disconnected.

This input is 5 V tolerant.

MOTOROLA

DSP56362 Advance Information

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