DSP56362/D View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

DSP56362/D

Digital audio applications requiring digital audio compression and decompression, sound field processing, acoustic equalization, and other digital audio algorithms.

Motorola => Freescale 

Overview

Features

Freescale Semiconductor, Inc.

• End-of-block-transfer interrupts

• Triggering from interrupt lines and all peripherals

– Phase-locked loop (PLL)

• Software programmable PLL-based frequency synthesizer for the core clock

• Allows change of low-power divide factor (DF) without loss of lock

• Output clock with skew elimination

– Hardware debugging support

• On-Chip Emulation (OnCE‘) module

• Joint Action Test Group (JTAG) test access port (TAP)

• Address trace mode reflects internal program RAM accesses at the external port

• On-Chip Memories

– Modified Harvard architecture allows simultaneous access to program and data memories

– 30720 x 24-bit on-chip program ROM1 (disabled in 16-bit compatibility mode)

– 6144 x 24-bit on-chip X-data ROM1

– 6144 x 24-bit on-chip Y-data ROM1

– Program RAM, instruction cache, X data RAM, and Y data RAM sizes are programmable

Instruction

Cache

Switch Program RAM

Mode

Size

.

Instruction

Cache Size

X Data RAM

Size

Y Data RAM

Size

Disabled

Enabled

Disabled

Enabled

Disabled

Disabled

Enabled

Enabled

3072 × 24-bit

2048 × 24-bit

5120 × 24-bit

4096 × 24-bit

0

1024 × 24-bit

0

1024 × 24-bit

5632 × 24-bit

5632 × 24-bit

5632 × 24-bit

5632 × 24-bit

5632 × 24-bit

5632 × 24-bit

3584 × 24-bit

3584 × 24-bit

– 192 x 24-bit bootstrap ROM (disabled in sixteen-bit compatibility mode)

• Off-Chip Memory Expansion

– Data memory expansion to 256K x 24-bit word memory for P, X, and Y memory using SRAM.

– Data memory expansion to 16M x 24-bit word memory for P, X, and Y memory using DRAM.

– External memory expansion port( twenty-four data pins for high speed external memory

access allowing for a large number of external accesses per sample)

– Chip select logic for glueless interface to SRAMs

– On-chip DRAM controller for glueless interface to DRAMs

• Peripheral and Support Circuits

– Enhanced serial audio interface (ESAI) includes:

• Six serial data lines, 4 selectable as receive or transmit and 2 transmit only.

• Master or slave capability

• I2S, Sony, AC97, and other audio protocol implementations

1.These ROMs may be factory programmed with data or programs provided by the application developer.

2

DSP56362 Advance Information

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

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