MAX812LEUS(2018) View Datasheet(PDF) - Maxim Integrated
Part Name
Description
Manufacturer
MAX812LEUS Datasheet PDF : 9 Pages
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MAX811/MAX812
4-Pin μP Voltage Monitors
with Manual Reset Input
Pin Description
PIN
MAX811 MAX812
1
1
2
—
—
2
3
3
4
4
NAME
GND
RESET
RESET
MR
VCC
FUNCTION
Ground
Active-Low Reset Output. RESET remains low while VCC is below the reset threshold or while
MR is held low. RESET remains low for the Reset Active Timeout Period (tRP) after the reset
conditions are terminated.
Active-High Reset Output. RESET remains high while VCC is below the reset threshold or while
MR is held low. RESET remains high for Reset Active Timeout Period (tRP) after the reset
conditions are terminated.
Manual Reset Input. A logic low on MR asserts reset. Reset remains asserted as long as MR
is low and for 180ms after MR returns high. This active-low input has an internal 20kΩ pull-up
resistor. It can be driven from a TTL or CMOS-logic line, or shorted to ground with a switch.
Leave open if unused.
+5V, +3.3V, or +3V Supply Voltage
Detailed Description
Reset Output
A microprocessor’s (μP’s) reset input starts the μP in a
known state. These μP supervisory circuits assert reset
to prevent code execution errors during power-up, power-
down, or brownout conditions.
RESET is guaranteed to be a logic low for VCC > 1V.
Once VCC exceeds the reset threshold, an internal timer
keeps RESET low for the reset timeout period; after this
interval, RESET goes high.
If a brownout condition occurs (VCC dips below the reset
threshold), RESET goes low. Any time VCC goes below
the reset threshold, the internal timer resets to zero, and
RESET goes low. The internal timer starts after VCC
returns above the reset threshold, and RESET remains
low for the reset timeout period.
The manual reset input (MR) can also initiate a reset. See
the Manual Reset Input section.
The MAX812 has an active-high RESET output that is the
inverse of the MAX811’s RESET output.
Manual Reset Input
Many μP-based products require manual reset capabil-
ity, allowing the operator, a test technician, or external
logic circuitry to initiate a reset. A logic low on MR asserts
reset. Reset remains asserted while MR is low, and for
the Reset Active Timeout Period (tRP) after MR returns
high. This input has an internal 20kΩ pull-up resistor, so
it can be left open if it is not used. MR can be driven with
TTL or CMOS-logic levels, or with open-drain/collector
outputs. Connect a normally open momentary switch from
MR to GND to create a manual-reset function; external
debounce circuitry is not required. If MR is driven from
long cables or if the device is used in a noisy environment,
connecting a 0.1μF capacitor from MR to ground provides
additional noise immunity.
Reset Threshold Accuracy
The MAX811/MAX812 are ideal for systems using a 5V
±5% or 3V ±5% power supply with ICs specified for 5V
±10% or 3V ±10%, respectively. They are designed to
meet worst-case specifications over temperature. The
reset is guaranteed to assert after the power supply
falls out of regulation, but before power drops below the
minimum specified operating voltage range for the system
ICs. The thresholds are pre-trimmed and exhibit tight dis-
tribution, reducing the range over which an undesirable
reset may occur.
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