FS6372(2000) View Datasheet(PDF) - AMI Semiconductor
Part Name
Description
Manufacturer
FS6372
(Rev.:2000)
(Rev.:2000)
AMI Semiconductor
FS6372 Datasheet PDF : 9 Pages
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FS6372
ROM-Based 3-PLL Clock Generator IC
AMERICAN MICROSYSTEMS, INC.
May 2000
Table 6: AC Timing Specifications
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ f rom typical.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
CLOCK
(MHz)
MIN.
TYP.
MAX. UNITS
Overall
Output Frequency *
VCO Frequency *
Rise Time *
Fall Time *
Tristate Enable Delay *
Tristate Disable Delay *
fO
fVCO
tr
tf
tPZL, tPZH
tPLZ, tPHZ
VDD = 5.5V
VDD = 3.6V
VDD = 5.5V
VDD = 3.6V
VO = 0.5V to 4.5V; CL = 15pF
VO = 0.3V to 3.0V; CL = 15pF
VO = 4.5V to 0.5V; CL = 15pF
VO = 3.0V to 0.3V; CL = 15pF
0.8
150
MHz
0.8
100
40
230
MHz
40
170
1.9
ns
1.6
1.8
ns
1.5
1
8
ns
1
8
ns
Clock Stabilization Time *
tSTB
Output active from power-up, via PD pin
100
µs
Clock Outputs (PLL A clock via CLK_A pin)
Duty Cycle *
Jitter, Long Term (σy(τ )) *
Jitter, Period (peak-peak) *
Ratio of pulse width (as measured from rising edge to next
falling edge at 2.5V) to one clock period
100
45
55
%
On rising edges 500µs apart at 2.5V relative to an ideal
clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50,
100
45
No other PLLs active
tj(LT)
On rising edges 500µs apart at 2.5V relative to an ideal
ps
clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50,
50
165
all other PLLs active (B=60MHz, C=40MHz, D=14.318MHz)
From rising edge to the next rising edge at 2.5V, CL=15pF,
fXIN=14.318MHz, NF=220, NR=63, NPx=50,
100
110
No other PLLs active
tj(∆P)
ps
From rising edge to the next rising edge at 2.5V, CL=15pF,
fXIN=14.318MHz, NF=220, NR=63, NPx=50, all other PLLs
50
390
active (B=60MHz, C=40MHz, D=14.318MHz)
5.23.00
ISO9001
6
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