FS6372(2000) View Datasheet(PDF) - AMI Semiconductor
Part Name
Description
Manufacturer
FS6372
(Rev.:2000)
(Rev.:2000)
AMI Semiconductor
FS6372 Datasheet PDF : 9 Pages
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AMERICAN MICROSYSTEMS, INC.
FS6372
ROM-Based 3-PLL Clock Generator IC
May 2000
Table 7: AC Timing Specifications, continued
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ f rom typical.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
CLOCK
(MHz)
MIN.
TYP.
MAX. UNITS
Clock Outputs (PLL B clock via CLK_B pin)
Duty Cycle *
Jitter, Long Term (σy(τ )) *
Jitter, Period (peak-peak) *
Ratio of pulse width (as measured from rising edge to
next falling edge at 2.5V) to one clock period
100
45
55
%
On rising edges 500µs apart at 2.5V relative to an ideal
clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63,
100
45
NPx=50, No other PLLs active
tj(LT)
On rising edges 500µs apart at 2.5V relative to an ideal
ps
clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63,
NPx=50, all other PLLs active (A=50MHz, C=40MHz,
60
75
D=14.318MHz)
From rising edge to the next rising edge at 2.5V,
CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50,
100
120
No other PLLs active
tj(∆P)
ps
From rising edge to the next rising edge at 2.5V,
CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, all
60
400
other PLLs active (A=50MHz, C=40MHz, D=14.318MHz)
Clock Outputs (PLL_C clock via CLK_C pin)
Duty Cycle *
Jitter, Long Term (σy(τ )) *
Jitter, Period (peak-peak) *
Ratio of pulse width (as measured from rising edge to
next falling edge at 2.5V) to one clock period
100
45
55
%
On rising edges 500µs apart at 2.5V relative to an ideal
clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63,
100
45
NPx=50, No other PLLs active
tj(LT)
On rising edges 500µs apart at 2.5V relative to an ideal
ps
clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63,
NPx=50, all other PLLs active (A=50MHz, B=60MHz,
40
D=14.318MHz)
105
From rising edge to the next rising edge at 2.5V,
CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50,
100
120
No other PLLs active
tj(∆P)
ps
From rising edge to the next rising edge at 2.5V,
CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, all
40
440
other PLLs active (A=50MHz, B=60MHz, D=14.318MHz)
Clock Outputs (Crystal Oscillator via CLK_D pin)
Duty Cycle *
Jitter, Long Term (σy(τ )) *
Jitter, Period (peak-peak) *
Ratio of pulse width (as measured from rising edge to
next falling edge at 2.5V) to one clock period
14.318
45
55
%
On rising edges 500µs apart at 2.5V relative to an ideal
clock, CL=15pF, fXIN=14.318MHz, No other PLLs active
14.318
20
tj(LT)
From rising edge to the next rising edge at 2.5V,
ps
CL=15pF, fXIN=14.318MHz, all other PLLs active
14.318
40
(A=50MHz, B=60MHz, C=40MHz)
From rising edge to the next rising edge at 2.5V,
CL=15pF, fXIN=14.318MHz, No other PLLs active
14.318
90
tj(∆P)
From rising edge to the next rising edge at 2.5V,
ps
CL=15pF, fXIN=14.318MHz, all other PLLs active
14.318
450
(A=50MHz, B=60MHz, C=40MHz)
5.23.00
ISO9001
7
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