11640-842(2000) View Datasheet(PDF) - AMI Semiconductor
Part Name
Description
Manufacturer
11640-842 Datasheet PDF : 6 Pages
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FS6183-04
1 PLL Clock Generator IC
AMERICAN MICROSYSTEMS, INC.
August 2000
Table 5: DC Electrical Specifications
Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP. MAX. UNITS
Overall
Supply Current, Dynamic, with Loaded
Outputs
IDD
fXTAL = 13.5MHz; CL = 10pF
Crystal Oscillator
Crystal Resonator Frequency
Crystal Loading Capacitance
fXTAL
Fundamental Mode
-
CL(xtal)
As seen by a crystal connected to XIN and
XOUT
Crystal Oscillator Drive Transconductance
Oscillator Source Current
gmOSC
IOH
VDD = 3.3V
VDD = 3.3V
V(XIN) = 0V, V(XOUT) = 0V
Oscillator Sink Current
IOL
VDD = 3.3V
V(XIN) = VDD, V(XOUT) = VDD
Clock Outputs (CLKA, CLKB, CLKC)
High-Level Output Source Current *
Low-Level Output Sink Current *
Output Impedance *
Short Circuit Source Current *
Short Circuit Sink Current *
IOH
VO = 2.0V
IOL
VO = 0.4V
zOH
VO = 0.1VDD; output driving high
zOL
VO = 0.1VDD; output driving low
IOSH
VO = 0V; shorted for 30s, max.
IOSL
VO = 3.3V; shorted for 30s, max.
20
13.5
18
16
-18
23
40
17
25
25
-55
55
mA
-
MHz
pF
mSiemens
mA
mA
mA
mA
Ω
mA
mA
Table 6: AC Timing Specifications
Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3σ from typical.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
CLOCK
(MHz)
MIN.
TYP.
MAX. UNITS
Clock Outputs (CLKx)
Duty Cycle *
Jitter, Absolute Period (pk-pk) *
Jitter, RMS Long Term (σy(τ)) *
thi / tclk; Measured at VDD/2
tj(∆P)
From rising edge to next rising edge at
VDD/2, CL = 10pF
tj(LT)
From 0-500µs at VDD/2, CL = 10pF
compared to ideal clock source
Rise Time *
tr
VDD = 3.3V; VO = 0.3V to 3.0V; CL = 10pF
Fall Time *
tf
VDD = 3.3V; VO = 3.0V to 0.3V; CL = 10pF
Output Frequency Synthesis Error
(unless otherwise noted in Frequency Table)
45
55
%
300
ps
150
ps
1
ns
1
ns
0
ppm
4
ISO9001
8.17.00
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