FS6207
VCXO Clock Generator IC
Table 6: AC Timing Specifications
Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3σ from typical.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
MIN. TYP. MAX. UNITS
Overall
Synthesis Error
Crystal Oscillator
Crystal Loading Capacitance
Crystal Drive Level
Clock Output (CLK)
Duty Cycle *
Jitter, Period (peak-peak) *
Jitter, Long Term (σy(τ)) *
Jitter, Long Term (σy(τ)) *
Rise Time *
Fall Time *
(unless otherwise noted in Frequency Table)
0
ppm
CL(xtal)
As seen by a crystal connected to XIN and XOUT
(@VXTUNE=mid-scale)
RXTAL=20Ω;
14
pF
200
uW
Ratio of high pulse width (as measured from rising edge to next falling
edge at VDD/2) to one clock period
45
55
%
tj(∆P)
From rising edge to next rising edge at VDD/2
150
ps
tj(LT)
From 0-500µs at VDD/2 compared to ideal clock
source (CLK =27MHz or 27.027MHz)
65
ps
tj(LT)
From 0-500µs at VDD/2 compared to ideal clock
source (CLK = 74.175MHz or 74.58MHz)
200
ps
tr
VDD = 3.3V; VO = 0.3V to 3.0V; CL = 10pF
tf
VDD = 3.3V; VO = 3.0V to 0.3V; CL = 10pF
1.2
ns
1.2
ns
5
ISO9001
2.28.02