FS6261-01 View Datasheet(PDF) - AMI Semiconductor
Part Name
Description
Manufacturer
FS6261-01 Datasheet PDF : 17 Pages
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January 2000
Table 2: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active-low pin
PIN
TYPE
NAME
DESCRIPTION
53, 54, 55
30
21, 22, 25, 26
41, 42, 45, 46
49, 50
36
9, 11, 12, 14,
15, 17, 18
8
37
35
2, 3
32, 33
28
34
39
31
23, 27
56
43, 47
51
10, 16
4
38
29
20, 24
52
40, 44
48
7, 13, 19
1
5
6
DO
APIC_0:2
Three low-skew (<250ps @ 1.25V) 2.5V 16.67MHz clock outputs for APIC bus timing. APIC
clocks are synchronous with CPU clocks but lag the CPU clocks by 1.5 to 4ns.
DO
CK48
One 3.3V 48MHz clock output for Universal Serial Bus (USB) timing
DO
CK66_0:3
Four 3.3V 66MHz AGP clock outputs. CK66 clocks are synchronous with CPU clocks but lag the
CPU clocks by 0 to 1.5ns.
DO
CPU_0:3
Four low-skew 2.5V 133/100MHz CPU clock outputs for host frequencies
DO
CPU/2_0:1
Two low-skew 2.5V clock outputs at half the CPU clock frequencies (66/50MHz)
DIU
CPU_STOP#
CPU_0:3 and CK66_0:3 clock output enable. Asynchronous, active-low disable stops all CPU
and CK66 clocks in the low state.
DO
PCI_1:7
Seven 3.3V PCI clock outputs. PCI clocks are synchronous with CPU clocks but lag the CK66
clocks by 1.5 to 4ns.
DO
PCI_F
One free-running 3.3V PCI clock output
DIU
PCI_STOP#
PCI_1:7 clock output enable. Asynchronous, active-low disable stops all PCI clocks in the low
state.
DIU
PWR_DWN#
Asynchronous active-low power-down signal shuts down oscillator, all PLLs, puts all clocks in
low state. Clock re-enable latency of ≤ 3ms.
DO
REF_0:1
Two buffered outputs of the 14.318MHz reference clock
DIU
SEL_0:1
Two frequency select inputs (see Table 4)
DI
SEL_133/100# Selects 133MHz or 100MHz CPU frequency (pull-up/pull-down must be provided externally)
DIU
SS_EN#
Spread spectrum enable. Active-low enable turns on the spread spectrum feature; a logic-high
turns off the spread spectrum modulation.
P
VDD
3.3V ± 10%
P
VDD_48
Power supply for 3.3V CK48 clock output
P
VDD_66
Power supply for 3.3V CK66_0:3 clock outputs
P
VDD_A
Power supply for 2.5V APIC_0:2 clock outputs
P
VDD_C
Power supply for 2.5V CPU_0:3 clock outputs
P
VDD_C2
Power supply for 2.5V CPU/2_0:1 clock outputs
P
VDD_P
Power supply for 3.3V PCI_1:7 and PCI_F clock outputs
P
VDD_R
Power supply for 3.3V REF_0:1 clock outputs
P
VSS
Ground
P
VSS_48
Ground for CK48 clock outputs
P
VSS_66
Ground for CK66_0:3 clock outputs
P
VSS_A
Ground for APIC_0:2 clock outputs
P
VSS_C
Ground for CPU_0:3 clock outputs
P
VSS_C2
Ground for CPU/2_0:1 clock outputs
P
VSS_P
Ground for PCI_1:7 and PCI_F clock outputs
P
VSS_R
Ground for REF_0:1 clock outputs
AI
XIN
14.318MHz crystal oscillator input. XIN can be driven by an external frequency source.
AO
XOUT
14.318MHz crystal oscillator output
,62
2
1.31.00
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