GM5115H View Datasheet(PDF) - Genesis Microchip

Part Name

Description

Manufacturer

GM5115H

OnPanel LCD Panel Controller

Genesis Microchip 

*** Genesis Microchip Confidential ***

gm5115/25 Preliminary Data Sheet

Pin Name

AVDD_IMB

REXT

AGND_IMB

VDD_RX2_2.5

GND_RX2

AGND_RX2

RX2+

RX2-

AVDD_RX2

VDD_RX1_2.5

GND_RX1

AGND_RX1

RX1+

RX1-

AVDD_RX1

VDD_RX0_2.5

GND_RX0

AGND_RX0

RX0+

RX0-

AVDD_RX0

RXC+

RXC-

AVDD_RXC

AGND_RXC

GND_RXPLL

VDD_RXPLL_2.5

CLKOUT

Pin Name

AVDD_RPLL

AVSS_RPLL

TCLK

XTAL

VDD_RPLL

VSS_RPLL

Table 2. DVI Input Port

No I/O Description

173 AP

174 AI

175 AG

176 P

177 G

178 AG

179 AI

180 AI

181 AP

182 P

183 G

184 AG

185 AI

186 AI

187 AP

188 P

189 G

190 AG

191 AI

192 AI

193 AP

194 AI

195 AI

196 AP

197 AG

198 G

199 AP

201 AO

Analog VDD (3.3V) for internal biasing circuits.

Must be bypassed with decoupling capacitors (as close as possible to the pin).

External reference resistor.

An external 1Kohm (1%) resistor should be connected from this pin to AVDD_IMB pin.

Analog GND for internal biasing circuits.

Must be connected directly to the ground plane.

VDD (2.5V) for DVI input pair 2 logic circuits. Must be bypassed with decoupling capacitor to

GND_RX2 pin (as close as possible to the pin).

GND for DVI input pair 2 logic circuits.

Must be connected directly to the ground plane.

Analog GND for DVI input pair 2 input buffer.

Must be connected directly to the analog ground plane.

DVI input pair 2

DVI input pair 2

Analog VDD (3.3V) for DVI input pair 2 input buffer. Must be bypassed with decoupling

capacitor to AGND_RX2 pin (as close as possible to the pin).

VDD (2.5V) for DVI input pair 1 logic circuits. Must be bypassed with decoupling capacitor to

GND_RX1 pin (as close as possible to the pin).

GND for DVI input pair 1 input buffer.

Must be connected directly to the analog ground plane.

Analog GND for DVI input pair 1 input buffer.

Must be connected directly to the analog ground plane.

DVI input pair 1

DVI input pair 1

Analog VDD (3.3V) for DVI input pair 1 input buffer. Must be bypassed with decoupling

capacitor to AGND_RX1 pin (as close as possible to the pin).

VDD (2.5V) for DVI input pair 0 logic circuits. Must be bypassed with decoupling capacitor to

GND_RX0 pin (as close as possible to the pin).

GND for DVI input pair 0 logic circuits.

Must be connected directly to the ground plane.

Analog GND for DVI input pair 0 input buffer.

Must be connected directly to the analog ground plane.

DVI input pair 0

DVI input pair 0

Analog VDD (3.3V) for DVI input pair 0 input buffer. Must be bypassed with decoupling

capacitor to AGND_RX0 pin (as close as possible to the pin).

DVI input clock pair

DVI input clock pair

Analog VDD (3.3V) for DVI input clock pair input buffer. Must be bypassed with 100pF

capacitor to AGND_RXC pin (as close as possible to the pin).

Analog GND for DVI input clock pair input buffer.

Must be connected directly to the analog ground plane.

Digital GND for the DVI receiver internal PLL.

Must be connected directly to the system ground plane.

Analog VDD (2.5V) for the DVI receiver internal PLL. Must be bypassed with a decoupling

capacitor to AGND_RXPLL pin (as close as possible to the pin).

For test purposes only. Do not connect.

Table 3. RCLK PLL Pins

No I/O Description

150 AP

149 AG

152 AI

151 AO

148 P

147 G

Analog power for the Reference DDS PLL. Connect to 3.3V supply. Must be bypassed with a

0.1uF capacitor to pin AVSS_RPLL (as close to the pin as possible).

Analog ground for the Reference DDS PLL.

Must be directly connected to the analog system ground plane.

Reference clock (TCLK) from the 14.3MHz crystal oscillator (see Figure 4), or from single-

ended CMOS/TTL clock oscillator (see Figure 7). This is a 5V-tolerant input. See Table 14.

Crystal oscillator output.

Digital power for RCLK PLL. Connect to 3.3V supply.

Digital ground for RCLK PLL.

June 2002

5

C5115-DAT-01H

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