GL652USB View Datasheet(PDF) - Genesys Logic

Part Name

Description

Manufacturer

GL652USB

USB 7 PORT HUB CONTROLLER

Genesys Logic 

GL652USB 7 PORT USB HUB CONTROLLER

5 REGISTER SUMMARY

MNEMONIC

DEVCTL

EVTFLG

RXCTL0

TXCTL0

TXCTL1

FFDAT

BUFCTL

PORTSEL

HUB_STAT_CHG

PORT_STATUS

BUS_PORT_DATA

HOST_CMD

ENP1_IND

TRXFLAG

LED_INIT

GPIOD

REV

DEVSTUS

OFFSET

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

DESCRIPTION

Device control register

USB function interrupt flag

Endpoint 0 RX control

Endpoint 0 TX control

Endpoint 1 TX control

Data buffer (FIFO) I/O port

Data buffer control register

Hub port to be configured

Hub status and status change indicator

Hub ports status indicator

Hub ports status change indicator

Host command to downstream ports

Endpoint 1 indicator

Downstream port traffic flag

LED initial state

General purpose I/O pin status

Chip revision

USB device address and configuration status

Register Description

Terminology:

R/O:

R/W:

R/W1C:

W/O:

read only

read / write

read / write “1” to clear

write only

DEVCTL

( offset 00, default = 00h )

R/W

R/W

R/W

R/O

R/O

USBRDY SFRAME

--

--

--

SELF

GANG

PWRDN

USBRDY

: 0 - USB interface is not ready. The device drives USB with SE0.

1 - USB interface is ready. The device stops driving USB with SE0.

After power-on reset, USBRDY is cleared and the device looks like

disconnected. Set USBRDY to ‘1’ to enable USB interface.

SFRAME

: short frame option for test purpose

Set SFRAME to ‘1’ will shorten frame length to 1/15 ms. It is to shorten the

time required for test.

PWRDN

: power down mode

In suspend state, firmware can set PWRDN to put the controller into power

down mo de. In this mode, the embedded micro-controller and most internal

activities are frozen. Hardware will automatically clear PWRDN upon

hardware reset or resume activities occur.

6

08/18/00

Revision 1.2

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