FDC37C669FR View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

Manufacturer

FDC37C669FR

Super I/O Floppy Disk Controller with Fast Infrared Support

SMSC -> Microchip 

QFP

PIN

NO.

82,92

80,90

85,87

NAME

nClear to

Send

nData Set

Ready

nData Carrier

Detect

DESCRIPTION OF PIN FUNCTIONS

SYMBOL

nCTS1

nCTS2

nDSR1

nDSR2

nDCD1

nDCD2

BUFFER

TYPE

I

I

I

DESCRIPTION

Active low Clear to Send inputs for the

serial port. Handshake signal which

notifies the UART that the modem is

ready to receive data. The CPU can

monitor the status of nCTS signal by

reading bit 4 of Modem Status Register

(MSR). A nCTS signal state change

from low to high after the last MSR read

will set MSR bit 0 to a 1. If bit 3 of

Interrupt Enable Register is set, the

interrupt is generated when nCTS

changes state. The nCTS signal has no

effect on the transmitter. Note: Bit 4 of

MSR is the complement of nCTS.

Active low Data Set Ready inputs for the

serial port. Handshake signal which

notifies the UART that the modem is

ready to establish the communication

link. The CPU can monitor the status of

nDSR signal by reading bit 5 of Modem

Status Register (MSR). A nDSR signal

state change from low to high after the

last MSR read will set MSR bit 1 to a 1.

If bit 3 of Interrupt Enable Register is set,

the interrupt is generated when nDSR

changes state. Note: Bit 5 of MSR is

the complement of nDSR.

Active low Data Carrier Detect inputs for

the serial port. Handshake signal which

notifies the UART that carrier signal is

detected by the modem. The CPU can

monitor the status of nDCD signal by

reading bit 7 of Modem Status Register

(MSR). A nDCD signal state change

from low to high after the last MSR read

will set MSR bit 3 to a 1. If bit 3 of

Interrupt Enable Register is set, the

interrupt is generated when nDCD

changes state. Note: Bit 7 of MSR is

the complement of nDCD.

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