FDC37C669FR View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

Manufacturer

FDC37C669FR

Super I/O Floppy Disk Controller with Fast Infrared Support

SMSC -> Microchip 

QFP

PIN

NO.

48-51

53-56

44

45

46

28-34

41-43,

97

21,52,

99

22,36,

96

NAME

Data Bus 0-7

nI/O Read

nI/O Write

Address

Enable

I/O Address

DMA Request

A, B, C

nDMA

Acknowledge

A, B, C

DESCRIPTION OF PIN FUNCTIONS

BUFFER

SYMBOL

TYPE

DESCRIPTION

HOST PROCESSOR INTERFACE

D0-D7

I/O24

The data bus connection used by the

host microprocessor to transmit data to

and from the chip. These pins are in a

high-impedance state when not in the

output mode.

nIOR

I

This active low signal is issued by the

host microprocessor to indicate a read

operation.

nIOW

I

This active low signal is issued by the

host microprocessor to indicate a write

operation.

AEN

I

Active high Address Enable indicates

DMA operations on the host data bus.

Used internally to qualify appropriate

address decodes.

A0-A10

I

These host address bits determine the

I/O address to be accessed during nIOR

and nIOW cycles. These bits are latched

internally by the leading edge of nIOR

and nIOW. All internal address decodes

use the full A0 to A10 address bits.

DRQ_A

DRQ_B

DRQ_C

O24 This active high output is the DMA

request for byte transfers of data

between the host and the chip. This

signal is cleared on the last byte of the

data transfer by the nDACK signal going

low (or by nIOR going low if nDACK was

already low as in demand mode).

nDACK_A

nDACK_B

nDACK_C

I

An active low input acknowledging the

request for a DMA transfer of data

between the host and the chip. This

input enables the DMA read or write

internally.

6

Share Link: