FDC37N958FR View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

Manufacturer

FDC37N958FR

Notebook I/O Controller with Enhanced Keyboard and System Control

SMSC -> Microchip 

FDC37N958FR OPERATING REGISTERS

HOST PROCESSOR INTERFACE

The address map, shown below in Table 3,

shows the set of operating registers and

addresses for each of the logical blocks of the

FDC37N958FR Ultra I/O controller. The base

addresses of the FDC, Parallel, Serial 1 and

Serial 2 ports can be moved via the configuration

registers.

The host processor communicates with the

FDC37N958FR through a series of read/write

registers. The range of base I/O port addresses

for these registers is shown in Table 3. Register

access is accomplished through programmed I/O

or DMA transfers. All registers are 8 bits. Most of

the registers support zero wait-state access

(NOWS). All host interface output buffers are

capable of sinking a minimum of 12 mA.

LOGICAL

DEVICE

NUMBER

0x00

0x03

Table 3 - FDC37N958FR Operating Register Addresses

LOGICAL

DEVICE

BASE I/O

RANGE

(NOTE3)

FIXED

BASE OFFSETS

FDC

[0x100:0x0FF8] +0 : SRA

+1 : SRB

ON 8 BYTE +2 : DOR

BOUNDARIES +3 : TSR

+4 : MSR/DSR

+5 : FIFO

+7 : DIR/CCR

Parallel [0x100:0x0FFC] +0 : Data / ecpAfifo

Port

ON 4 BYTE +1 : Status

BOUNDARIES +2 : Control

(EPP Not

supported)

or

[0x100:0x0FF8]

ON 8 BYTE

+400h : cfifo / ecpDfifo

tfifo / cnfgA

+401h : cnfgB

+402h : ecr

BOUNDARIES

(all modes

supported,

EPP is only

available when

the base

address is on an

8-byte boundary)

ISA

CYCLE

TYPE

NOWS

Std. ISA I/O

SMSC DS – FDC37N958FR

Page 14

Rev. 09/01/99

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