SSD0817Z(2002) View Datasheet(PDF) - Solomon Systech
Part Name
Description
Manufacturer
SSD0817Z Datasheet PDF : 43 Pages
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DIE PAD ARRANGEMENT
125
ROW10
126
ROW9
ROW8
ROW7
ROW6
ROW5
ROW4
ROW3
ROW2
ROW1
ROW0
ICONS
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG92
SEG93
SEG94
SEG95
SEG96
SEG97
SEG98
SEG99
SEG100
SEG101
SEG102
SEG103
ROW32
ROW33
ROW34
ROW35
ROW36
ROW37
ROW38
ROW39
ROW40
ROW41
ROW42
ROW43
255
254
277
150µm 150µm 150µm
150µm 150µm 150µm
104
T5
103
T4
T3
IIC2
VSS
IRS
VDD
X
X
C1
VSS
C0
/IIC1
TEST7
VSS
CLS
Center (-3876.1625, 323.6625)
Center (2751.9625, 323.6625)
M/S
VDD
VF
VL6
VL6
VL6
VL5
50 µm 200
50 µm 200
VL5
VL5
VL4
VL4
X µm
X µm
VL4
VEE
(-3878.7, 237.475)
(2755.725, 237.475)
VL3
VL3
VL3
VL2
VL2
VL2
VDD
C4N
C4N
C4N
C2P
C2P
C2P
C2N
C2N
Note:
1. The gold bumps face up in
C2N
VEE
this diagram
C1N
C1N
C1N
2. All dimensions in µm and
C1P
C1P
(0,0) is the center of the
C1P
C3N
chip
C3N
C3N
T2
VEE
VEE
Die Size:
8.66mm X 1.48mm
VEE
VEE
Die Thickness: 675 +/- 25 um
VEE
VEE
VSS1
Bump Pitch: 60 um [Min]
VSS1
VSS1
Bump Height: Nominal 18 um
VSS1
VSS1
VSS
VSS
VSS
T1
T0
VDD
VDD
VDD
VDD
Gold Bump Alignment Mark
VDD
VDD
This alignment mark contains gold
VDD
TEST6
TEST5
SA0
SCL
bump for IC bumping process
alignment and IC identifications. No
TEST4
TEST3
conductive tracks should be laid
SDAin
SDAout
underneath this mark to avoid short
VDD
TEST2
circuit.
TEST1
VSS
TEST0
96 µm 78 µm 72 µm
VEE
VEE
/RES
VDD
CS2
/CS1
VSS
/DOF
CL
M
MSTAT
PIN #1
276
Center (3875.55, 149.275)
SOLOMON
Figure 2 – SSD0817 Pin Assignment
Rev 1.0
03/2002
420 µm
4
SSD0817 Series
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