SSD0817Z View Datasheet(PDF) - Solomon Systech

Part Name

Description

Manufacturer

SSD0817Z

LCD Segment / Common Driver with Controller

Solomon Systech  

voltage level is used for internal referencing only. The voltage level at VEE pins is not used for driving

external circuitry.

C1P, C1N, C2N, C2P C3N and C4N

When internal DC-DC voltage converter is used, external capacitor(s) is/are connected between these

pins. Different connections result in different DC-DC converter multiple factors, for example, 2X, 3X,

4X or 5X. Please refer to the voltage converter section in the functional block description for detail

description.

VL2, VL3, VL4 and VL5

These pins are outputs with voltage levels equal to the LCD driving voltage. All these voltage levels

are referenced to VDD. The voltage levels can be supplied externally or generated by the internal bias

divider. The bias divider is turned on once the output op-amp buffers are enabled. Please refer to the

Set Power Control Register command for detail description.

The voltage potential relationship is given as: VDD > VL2 > VL3 > VL4 > VL5 > VL6

In addition, assume the bias factor is known as a,

VL2 - VDD = 1/a * (VL6 - VDD)

VL3 - VDD = 2/a * (VL6 - VDD)

VL4 - VDD = (a-2)/a * (VL6 - VDD)

VL5 - VDD = (a-1)/a * (VL6 - VDD)

VL6

This pin outputs the most negative LCD driving voltage level. The VL6 can be supplied externally or

generated by the internal regulator. Please refer to the Set Power Control Register command for

detail description.

M/ S

This pin is the master/slave mode selection input. When this pin is pulled high, master mode is

selected. CL, M, MSTAT and DOF signals will become output pins of the slave devices.

When this pin is pulled low, slave mode is selected. CL, M, DOF will become input pins. The CL, M,

DOF signals are received from the master device. The MSTAT pin will stay at high impedance state.

VF

This pin is the input of the built-in voltage regulator for generating VL6. When external resistor network

is selected (IRS pulled low) to generate the LCD driving level, VL6, two external resistors should be

added. R1 should be connected between VDD and VF. R2 should be connected between VF and VL6.

CLS

This pin is the internal clock enable pin. When this pin is pulled high, the internal clock is enabled.

The internal clock will be disabled when CLS is pulled low. Under such circumstances, an external

clock source must be fed into the CL pin.

IIC1, IIC2

These pins are I2C-bus interface selection inputs. The IIC communication interface is enabled only

when IIC1is pulled low and IIC2 is pulled high.

Solomon Systech

Jan 2003 P 8/40 Rev 1.3

SSD0817

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