SSD1810 View Datasheet(PDF) - Solomon Systech

Part Name

Description

Manufacturer

SSD1810

LCD Segment / Common Driver with Controller

Solomon Systech  

PIN DESCRIPTIONS

MODE

This pin is display mode select input.

MODE = 1: Set to 34-mux display.

MODE = 0 or N/C: Set to 32-mux display.

FR

This pin is the frame signal output. The voltage output

from this pin is either VSS or VDD. This voltage will toggle

once per frame.

FRS

This pin is used together with FR in for static drive (indica-

tor) output. Voltage level output from this pin is also either

VSS or VDD. After power-on or after Set Indicator Off com-

mand is issued, this pin will be same phase signal to FR. If

Set Indicator On command is sent to the chip, a out-of-phase

to FR signal will be output.

CL

This pin is the display clock output.

CS1, CS2

These pin are chip select inputs. The chip is enabled for

MCU communication only when both CS1 is pulled low and

CS2 is pulled high.

RES

This pin is reset signal input. Initialization of the chip is

started once this pin is pulled low. Minimum pulse width for

completing the reset procedure is 1µs.

D/C

This pin is Data/Command control pin. When the pin is

pulled high, the data at D7-D0 is treated as display data.

When the pin is pulled low, the data at D7-D0 will be trans-

ferred to the command register. Details relationship with other

MCU interface signals, please refer to the Timing Character-

istics Diagrams.

R/W(WR)

This pin is MCU interface input. When interfacing to a

6800-series microprocessor, this pin will be used as Read/

Write (R/W) selection input. Read mode will be carried out

when this pin is pulled high and write mode when low.

When interfacing to an 8080-microprocessor, this pin will

be the Write (WR) input. Data write operation is initiated when

this pin is pulled low when the chip is selected.

E(RD)

This pin is MCU interface input. When interfacing to an

6800-series microprocessor, this pin will be used as the En-

able (E) signal. Read/write operation is initiated when this pin

is pulled high when the chip is selected.

When connecting to an 8080-microprocessor, this pin re-

ceives the Read (RD) signal. Data read operation is initiated

when this pin is pulled low when the chip is selected.

D7-D0

These pins are the 8-bit bi-directional data bus to be con-

nected to the MCU in parallel interface mode. D7 is the MSB

while D0 is the LSB.

When serial mode is selected, D7 is the serial data input

(SDA) and D6 is the serial clock input (SCK).

VDD

Chip’s Power Supply pin. This is also the reference for the

DC-DC Converter output and LCD driving voltages.

VSS

Ground. A reference for the logic pins.

VEE

This is the most negative voltage supply pin of the chip. It

can be supplied externally or generated by the internal DC-DC

converter, by turning on the internal voltage booster option in

the Set Power Control Register command.

When using internal DC-DC converter as generator, volt-

age at this pin is for internal reference only. It CANNOT be used

for driving external circuitries.

C3N, C1P, C1N, C2N and C2P

When internal DC-DC voltage converter is used, external

capacitor(s) is/are connected between these pins. Different con-

nection will result in different DC-DC converter multiple factor,

2X, 3X or 4X. Detail connections please refer to voltage convert-

er section in the functional block description.

VL2, VL3, VL4 and VL5

These are the LCD driving voltage levels. All these levels

are referenced to VDD.

They can be supplied externally or generated by the inter-

nal bias divider, by turning on the output op-amp buffers op-

tion in the Set Power Control Register command.

The potential relation of these pins are given as:

VDD > VL2 > VL3 > VL4 > VL5 > VL6

and with bias factor, a,

VL2 - VDD = 1/a * (VL6 - VDD)

VL3 - VDD = 2/a * (VL6 - VDD)

VL4 - VDD = (a-2)/a * (VL6 - VDD)

VL5 - VDD = (a-1)/a * (VL6 - VDD)

VL6

This pin is the most negative LCD driving voltage. It can be

supplied externally or generated by turning on the internal reg-

ulator option in the Set Power Control Register command.

VF

This pin is the input of the built-in voltage regulator for gen-

erating VL6.

When external resistor network is selected (IRS pulled low)

to generate the LCD driving level, VL6, two external resistors, R1

and R2, should be connected between VDD and VF, and VF and

VL6, respectively (see application circuit diagrams).

SSD1810/A

10

REV 1.1

05/01

SOLOMON

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