SSD1882(2001) View Datasheet(PDF) - Solomon Systech

Part Name

Description

Manufacturer

SSD1882
(Rev.:2001)

MLA ROW (COMMON) DRIVER

Solomon Systech  

PIN DESCRIPTIONS

VCC, +V1, VC, -V1 (Power Pin)

VCC is the power supply pin to the logic system. The

voltage range is 2.7V to 5.5V with respect to the -V1 pin.

+V1, VC and -V1 are power supply pins to the LCD driving

system. Their relationship is +V1≥VC≥VCC≥-V1.

YD (Input Pin)

This input pin is used as a signal to start a frame and

to reset the column address for writing. (Refer to Note 1)

LP (Input Pin)

This is an input pin for display data latch clock. The

display data is latched at the falling edge of LP. (Refer to

Note 1)

FR (Input Pin)

This is an input pin and is used to change the LCD

driving waveform polarity. If power chip SSD1730 is used,

the output FR from the power chip should be connected to

the FR pin of the row driver. (Refer to Note 1)

F1, F2 (Input Pin)

These are input pins and are used as driver pattern

select signals. These two signals are generated by a col-

umn driver. If a display system is formed by the column

driver SSD1870 and the row driver SSD1882, outputs F10

and F20 from the column driver should be connected to F1

and F2 of the row driver respectively. (Refer to Note 1)

DOFF (Input Pin)

This is an input pin and is used to control the display.

When it is set at “L” level, all common outputs are forced to

VC level and the LC display will be forced to blank, howev-

er, the contents of the latches are maintained. In normal

display operation, it is set to “H” level. (Refer to Note 1)

SEL (Input Pin)

SSD1882 can be configured as 200 or 240 common

outputs depending on the logic level of input pin SEL.

When SEL is set at “L” level, 240 outputs are chosen

and COM0 to COM239 will be used. When SEL is set at

“H” level, 200 outputs are chosen and only COM20 to

COM219 will be used.

CIO1, CIO2 (I/O Pin)

These are I/O pins and they can be configured as an

input or an output by the signal SHL. When SHL is set at

“L” level, CIO1 is input and CIO2 is output. When SHL is

set at “H” level, CIO1 is output and CIO2 is input. The out-

put transition occurs on the falling edge of LP. (Refer to

Note 1)

SHL (Input Pin)

This is an input pin and is used to select the output shift di-

rection and to configure CIO1 and CIO2. The following table

shows the relationship between SEL, SHL, CIO1, CIO2 and the

output shift direction.

SEL = L (240 common outputs)

SHL

Output Shift Direction CIO1 CIO2

L COM0 ------> COM239

H COM239 ------> COM0

Input Output

Output Input

SHL

SEL = H (200 common outputs)

Output Shift Direction CIO1

CIO2

L COM20 ------> COM219

H COM219 ------> COM20

Input Output

Output Input

LSEL (Input Pin)

This is an input pin to select 1P Operation or 1/2P Opera-

tion. That can cope with different LCD having different response

time.

When LSEL is set at “L” level, 1P Normal Operation is se-

lected. When LSEl is set at “H” level, 1/2P Operation is selected.

CSEL (Input Pin)

This is a chip select signal input. When only one common

driver is used, CSEL should be set at “L” level. When multiple

common drivers are used, CSEL of the leading chip must be tied

to “L” level and that of other chips must be tied to “H” level.

TEST1 (Input Pin)

This is a reserved pin and it must be set at “L” level in the

normal operation.

TEST2 (Input Pin, only exists on gold-bumped die)

This is a reserved pin and it must be set at “L” level in the

normal operation.

COM0-COM239 (Output Pin)

These are output pins and provide common driving signals

to the LCD panel. Output transition occurs at the falling edge of

LP.

Note 1 : If an MLA LCD system is formed by SSD1882 row driver, SSD1870 column driver and SSD1730 power chip, 1nF capacitor

is necessary for capacitor coupling between SSD1882 and SSD1870 signals. Refer to the Application example for circuit connection.

SSD1882

8

Rev1.1

05/2001

SOLOMON

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