SSD1854U View Datasheet(PDF) - Solomon Systech

Part Name

Description

Manufacturer

SSD1854U

LCD Segment / Common Driver with Controller CMOS

Solomon Systech  

7 FUNCTIONAL BLOCK DESCRIPTIONS

7.1 Command Decoder and Command Interface

This module determines whether the input data is interpreted as data or command. Data is

directed to this module based upon the input of the D/ C pin. If D/ C is high, data is written to

Graphic Display Data RAM (GDDRAM). If D/ C is low, the input at D0-D15 is interpreted as a

Command and it will be decoded and written to the corresponding command register.

Reset is of the same function as Power ON Reset (POR). Once RES receives a negative reset

pulse of about 1us, all internal circuitry will be back to its initial status. Refer to Command

Description section for more information.

7.2 MPU Parallel 6800-series Interface

The parallel interface consists of 8/16 data pins (D0 - D15), R/W( WR ), D/ C , E( RD ) and CS .

R/ W ( WR ) input High indicates a read operation from the Graphic Display Data RAM

(GDDRAM) or the status register. R/W( WR ) input Low indicates a write operation to Display

Data RAM or Internal Command Registers depending on the status of D/ C input. The E( RD )

and CS input serves as data latch signal (clock) when they are high and low respectively. Refer

to Figure 9 of parallel timing characteristics for Parallel Interface Timing Diagram of 6800-series

microprocessors.

In order to match the operating frequency of display RAM with that of the microprocessor, some

pipeline processing is internally performed which requires the insertion of a dummy read before

the first actual display data read. This is shown in Figure 3 below.

R/W(WR)

E(RD)

data bus

N

writ e column address

dummy read

n

data read1

n+1

data read 2

n+2

data read 3

Figure 3 – Display Data Read with the insertion of Dummy Read

7.3 MPU Parallel 8080-series Interface

The parallel interface consists of 8/16 data pins (D0-D15), R/W( WR ), E( RD ), D/ C and CS . The

CS input serves as data latch signal (clock) when it is low. Whether it is display data or status

register read is controlled by D/ C . R/W( WR ) and E( RD ) input indicates a write or read cycle

when CS is low. Refer to Figure 10 of parallel timing characteristics for Parallel Interface Timing

Diagram of 8080-series microprocessor.

Similar to 6800-series interface, a dummy read is also required before the first actual display

data read.

11

SSD1854

Series

Rev 1.0

08/2002

SOLOMON

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