SSD1901 View Datasheet(PDF) - Solomon Systech

Part Name

Description

Manufacturer

SSD1901

TFT Graphics Controller

Solomon Systech  

REG[07h] Vertical Window Size Register (LSB)

Address = 1FF87h

Vertical

Window

Size Bit 7

Vertical

Window

Size Bit 6

Vertical

Window

Size Bit 5

Vertical

Window

Size Bit 4

Vertical

Window

Size Bit 3

Vertical

Window

Size Bit 2

Vertical

Window

Size Bit 1

Read/Write

Vertical

Window

Size Bit 0

REG[08h] Vertical Window Size Register (MSB)

Address = 1FF88h

Read/Write

Vertical

Vertical

0

0

0

0

0

0

Window

Window

Size Bit 9

Size Bit 8

REG[07h] bit 7-0

REG[08h] bit 1-0

Vertical Window Size Bits [9:0]

These bits determine the vertical resolution of the window area for Window features. This register is effec-

tive in Window features is selected (REG[00h] bit 4 = 1)

This register must be programmed with a value calculated as follows :

REG[08h],REG[07h] = VerticalWindowSize(lines) - 1

3FFh is the maximum value of this register for a vertical resolution of 1024 lines.

REG[09h] Look-Up Table Address for Blinking Register

Address = 1FF89h

LUT

Address

Bit 7

LUT

Address

Bit 6

LUT

Address

Bit 5

LUT

Address

Bit 4

LUT

Address

Bit 3

LUT

Address

Bit 2

LUT

Address

Bit 1

Read/Write

LUT

Address

Bit 0

bits 7-0

LUT Address for Blinking Bits [7:0]

This register control the index of the Look-Up Tables (LUT) for Window Blinking. The SSD1901 has three

256-position, 4-bit wide LUTs, one for each red, green, and blue - refer to Figure 5.4 "Look - Up Table" for

the architecture. This register is effective in Window Blinking only (REG[00h] bit 4,1 = 1)

REG[0Ah] Frame Period for Blinking Register

Address = 1FF8Ah

Frame

Period Bit 7

Frame

Period Bit 6

Frame

Period Bit 5

Frame

Period Bit 4

Frame

Period Bit 3

Frame

Period Bit 2

Frame

Period Bit 1

Read/Write

Frame

Period Bit 0

bits 7-0

Frame Period for Blinking Bits [7:0]

This register control the number of frame period for Window Blinking. This register is effective in Window

Blinking only (REG[00h] bit 4,1 = 1)

This register is programmed as follows :

REG[0Ah] = OnFramePeriod - 1 = OffFramePeriod - 1

REG[0Bh] Input Clock Register

Address = 1FF8Bh

CLK

Selection

Clock Divide Clock Divide

Bit 6

Bit 5

Clock Divide

Bit 4

Clock Divide

Bit 3

Clock Divide

Bit 2

Clock Divide

Bit 1

Read/Write

Clock Divide

Bit 0

SSD1901

10

REV 1.1

07/2001

SOLOMON

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