74LVC74A(2020) View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
74LVC74A
(Rev.:2020)
(Rev.:2020)
NXP Semiconductors.
74LVC74A Datasheet PDF : 17 Pages
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Nexperia
74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
6. Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care
Input
nSD
nRD
nCP
nD
L
H
X
X
H
L
X
X
L
L
X
X
Output
nQ
H
L
H
Table 4. Function table
H = HIGH voltage level; L = LOW voltage level;
↑ = LOW-to-HIGH transition; Qn+1 = state after the next LOW-to-HIGH CP transition
Input
Output
nSD
nRD
nCP
nD
H
H
↑
L
nQn+1
L
H
H
↑
H
H
nQ
L
H
H
nQ n+1
H
L
7. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max Unit
VCC
IIK
VI
IOK
VO
IO
ICC
IGND
Tstg
Ptot
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
VI < 0 V
VO > VCC or VO < 0 V
VO = 0 V to VCC
Tamb = -40 °C to +125 °C
-0.5
-50
[1] -0.5
-
[2] -0.5
-
-
-100
-65
[3]
-
+6.5 V
-
mA
+6.5 V
±50 mA
VCC + 0.5 V
±50 mA
100 mA
-
mA
+150 °C
500 mW
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SOT108-1 (SO14) package: Ptot derates linearly with 10.1 mW/K above 100 °C.
For SOT337-1 (SSOP14) package: Ptot derates linearly with 7.3 mW/K above 81 °C.
For SOT402-1 (TSSOP14) package: Ptot derates linearly with 7.3 mW/K above 81 °C.
For SOT762-1 (DHVQFN14) package: Ptot derates linearly with 9.6 mW/K above 98 °C.
74LVC74A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 18 June 2020
© Nexperia B.V. 2020. All rights reserved
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