74LVC74ABQ View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
74LVC74ABQ Datasheet PDF : 16 Pages
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NXP Semiconductors
74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
6. Functional description
Table 3. Function table[1]
Input
nSD
nRD
nCP
nD
L
H
X
X
H
L
X
X
L
L
X
X
[1] H = HIGH voltage level
L = LOW voltage level
X = don’t care
Output
nQ
nQ
H
L
L
H
H
H
Table 4. Function table[1]
Input
nSD
nRD
nCP
nD
H
H
↑
L
H
H
↑
H
[1] H = HIGH voltage level
L = LOW voltage level
↑ = LOW-to-HIGH transition
Qn+1 = state after the next LOW-to-HIGH CP transition
X = don’t care
7. Limiting values
Output
nQn+1
L
H
nQn+1
H
L
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max
Unit
VCC
IIK
VI
IOK
VO
IO
ICC
IGND
Tstg
Ptot
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
VI < 0 V
VO > VCC or VO < 0 V
VO = 0 V to VCC
Tamb = −40 °C to +125 °C
−0.5
−50
[1] −0.5
-
[2] −0.5
-
-
−100
−65
[3] -
+6.5
V
-
mA
+6.5
V
±50
mA
VCC + 0.5 V
±50
mA
100
mA
-
mA
+150
°C
500
mW
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SO14 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K.
For (T)SSOP14 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 °C the value of Ptot derates linearly with 4.5 mW/K.
74LVC74A_6
Product data sheet
Rev. 06 — 4 June 2007
© NXP B.V. 2007. All rights reserved.
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