AT26DF041-MU View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
AT26DF041-MU Datasheet PDF : 20 Pages
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AT26DF041
5.2.5
5.2.6
then the first six pages of the sector must be “refreshed” within 10,000 cumulative page erase
operations to that sector. The pages used to store the changing data do not need to be
“refreshed” provided that the pages are updated sequentially or in such a fashion that guaran-
tees that each page is rewritten on a fairly even basis.
Block Erase (2 Kbytes)
A block of 2 Kbytes (eight pages) can be erased at one time allowing the Page Program or
Byte Program commands to be utilized to reduce programming times when writing large
amounts of data to the device. To perform a 2 KB Block Erase, an opcode of 50H must be
loaded into the device, followed by the 24-bit address sequence. As stated previously,
address bits A23 - A19 are ignored. In addition, address bits A10 - A0 are ignored since a full
block of eight pages is being erased, but any address within the block can be used. When a
low-to-high transition occurs on the CS pin, the part will erase the selected block of eight
pages to 1s. The erase operation is internally self-timed and should take place in a maximum
time of tBE1. During this time, the status register will indicate that the part is busy.
Block Erase (4 Kbytes)
A block of 4 Kbytes (16 pages) can be erased at one time allowing the Page Program or Byte
Program commands to be utilized to reduce programming times when writing large amounts of
data to the device. To perform a 4 KB Block Erase, an opcode of 20H must be clocked into the
device followed by the 24 bit address sequence (A23 - A0), of which address bits A23 - A19
are ignored since the upper address limit of the device is 07FFFFh. In addition, address bits
A11 - A0 are ignored since a full block of 16 pages is being erased; however, any address
within the block can be used to specify which block to erase. When the CS pin is deasserted,
the device will erase the selected block of 16 pages to logical 1s. The erase operation is inter-
nally self-timed and should take place in a maximum of time of tBE2. During this time, the status
register will indicate that the device is busy.
7
3495B–DFLSH–8/05
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