AT26DF081A-SU(2005) View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
AT26DF081A-SU Datasheet PDF : 36 Pages
| |||
AT26DF081A [Preliminary]
The device also incorporates an intelligent programming algorithm that can detect when a byte
location fails to program properly. If a programming error arises, it will be indicated by the EPE
bit in the Status Register.
The Byte/Page Program mode is the default programming mode after the device powers-up or
resumes from a device reset.
Figure 8-1. Byte Program
CS
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12
29 30 31 32 33 34 35 36 37 38 39
OPCODE
ADDRESS BITS A23-A0
DATA IN
0 0 0 0 0 0 1 0AAAAAA
MSB
MSB
AAADDDDDDDD
MSB
HIGH-IMPEDANCE
Figure 8-2. Page Program
CS
SCK
SI
SO
0123456789
29 30 31 32 33 34 35 36 37 38 39
OPCODE
ADDRESS BITS A23-A0
DATA IN BYTE 1
0 0 0 0 0 0 1 0AAA
MSB
MSB
AAADDDDDDDD
MSB
HIGH-IMPEDANCE
DATA IN BYTE n
DDDDDDDD
MSB
8.2 Sequential Program Mode
The Sequential Program Mode improves throughput over the Byte/Page Program command
when the Byte/Page Program command is used to program single bytes only into consecutive
address locations. For example, some systems may be designed to program only a single byte
of information at a time and cannot utilize a buffered Page Program operation due to design
restrictions. In such a case, the system would normally have to perform multiple Byte Program
operations in order to program data into sequential memory locations. This approach can add
considerable system overhead and SPI bus traffic.
The Sequential Programming Mode helps reduce system overhead and bus traffic by incorporat-
ing an internal address counter that keeps track of the byte location to program, thereby
eliminating the need to supply an address sequence to the device for every byte to program.
When using the Sequential Program mode, all address locations to be programmed must be in
the erased state. Before the Sequential Program mode can first be entered, the Write Enable
command must have been previously issued to the device to set the WEL bit of the Status Reg-
ister to a logical “1” state.
9
3600A–DFLASH–11/05
Share Link: 