SAF-C167CR-16RM View Datasheet(PDF) - Siemens AG
Part Name
Description
Manufacturer
SAF-C167CR-16RM Datasheet PDF : 67 Pages
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C167CR-16RM 20Dec96@09:25h Intermediate Version
AC Characteristics
Demultiplexed Bus
VCC = 5 V ± 10 %; VSS = 0 V
TA = 0 to +70 °C
for SAB-C167CR-16RM
TA = -40 to +85 °C for SAF-C167CR-16RM
TA = -40 to +125 °C for SAK-C167CR-16RM
CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF
CL (for Port 6, CS) = 100 pF
ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20-MHz CPU clock without waitstates)
Parameter
ALE high time
Address setup to ALE
ALE falling edge to RD,
WR (with RW-delay)
ALE falling edge to RD,
WR (no RW-delay)
RD, WR low time
(with RW-delay)
RD, WR low time
(no RW-delay)
RD to valid data in
(with RW-delay)
RD to valid data in
(no RW-delay)
ALE low to valid data in
Address to valid data in
Data hold after RD
rising edge
Data float after RD rising
edge (with RW-delay 1))
Data float after RD rising
edge (no RW-delay 1))
Data valid to WR
Data hold after WR
Symbol
t5 CC
t6 CC
t8 CC
t9 CC
t12 CC
t13 CC
t14 SR
t15 SR
t16 SR
t17 SR
t18 SR
Max. CPU Clock
= 20 MHz
min.
max.
15 + tA –
10 + tA –
15 + tA –
-10 + tA –
40 + tC –
65 + tC –
–
30 + tC
–
55 + tC
–
55
+ tA + tC
–
70
+ 2tA + tC
0
–
Variable CPU Clock
1/2TCL = 1 to 20 MHz
min.
max.
TCL - 10 + tA –
TCL - 15 + tA –
TCL - 10
–
+ tA
-10
–
+ tA
2TCL - 10 –
+ tC
3TCL - 10 –
+ tC
–
2TCL - 20
+ tC
–
3TCL - 20
+ tC
–
3TCL - 20
+ tA + tC
–
4TCL - 30
+ 2tA + tC
0
–
t20 SR –
t21 SR –
t22 CC 25 + tC
t24 CC 15 + tF
35 + tF
15 + tF
–
–
–
2TCL - 15
+ 2tA + tF 1)
–
TCL - 10
+ 2tA + tF 1)
2TCL - 25 –
+ tC
TCL - 10 + tF –
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Semiconductor Group
54
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