CS61535A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CS61535A Datasheet PDF : 48 Pages
| |||
CS61535A
THEORY OF OPERATION
Enhancements in CS61535A
The CS61535A provides higher performance and
more features than the CS61535 including:
• 50% lower power consumption,
• Internally matched transmitter output imped-
ance for improved signal quality,
• Optional AMI, B8ZS, HDB3 encoder/decoder
or external line coding support,
• Receiver AIS (unframed all ones) detection,
• ANSI T1.231-1993 compliant receiver Loss
of Signal (LOS) handling,
• Transmitter TTIP and TRING outputs are
forced low when TCLK is static,
• The Driver Performance Monitor operates
over a wider range of input signal levels.
• Elimination of the requirement that a refer-
ence clock be input on the ACLKI pin.
Existing designs using the CS61535 can be converted
to the higher performance, pin-compatible CS61535A
if the transmit transformer is replaced by a pin-com-
patible transformer with a new turns ratio and the 4.4
Ω resistor used in E1 75 Ω applications is shorted.
Introduction to Operating Modes
The CS61535A supports three operating modes
which are selected by the level of the MODE pin
MODE
EXTENDED
HARDWARE HARDWARE
HOST
MODE-PIN
INPUT LEVEL
<0.2V
FLOAT, or
2.5V
>(RV+) - 0.2V
CONTROL
METHOD
INDIVIDUAL
CONTROL
LINES
INDIVIDUAL
CONTROL
LINES &
PARALLEL
CHIP
SELECT
SERIAL
µ-PROCESSOR
PORT
LINE CODE
ENCODER &
DECODER
NONE
AMI,
B8ZS,
HDB3
NONE
AIS DETECTION
NO
YES
NO
DRIVER
PERFORM-
YES
NO
ANCE MONITOR
YES
Table 1. Differences in Operating Modes
10
as shown in Tables 1 and 2, Figure 7, and Figures
A1-A3 of the Applications section.
The CS61535A modes are Hardware Mode, Ex-
tended Hardware Mode, and Host Mode. In
Hardware and Extended Hardware Modes, discrete
pins are used to configure and monitor the device.
The Extended Hardware Mode provides a parallel
chip select input which latches the control inputs
allowing individual ICs to be configured using a
common set of control lines. In the Host Mode, an
external processor monitors and configures the de-
vice through a serial interface. There are thirteen
multi-function pins whose functionality is deter-
mined by the operating mode (see Table 2).
Transmitter
The transmitter takes data from a T1 (or E1) ter-
minal, attenuates jitter, and produces pulses of
appropriate shape. The transmit clock, TCLK,
and transmit data, TPOS & TNEG or TDATA, are
supplied synchronously. Data is sampled on the
falling edge of the input clock, TCLK.
Either T1 (DSX-1 or Network Interface) or E1
G.703 pulse shapes may be selected. Pulse shap-
ing and signal level are determined by "line
length select" inputs as shown in Table 3. The
FUNCTION PIN
TRANSMITTER 3
4
6
7
RECEIVER/DPM 11
17
18
18
23
CONTROL
24
25
26
27
28
HARDWARE
TPOS
TNEG
RNEG
RPOS
DPM
MTIP
MRING
-
LEN0
LEN1
LEN2
RLOOP
LLOOP
TAOS
MODE
EXTENDED
HARDWARE
TDATA
TCODE
BPV
RDATA
AIS
RCODE
-
PCS
LEN0
LEN1
LEN2
RLOOP
LLOOP
TAOS
Table 2. Pin Definitions
HOST
TPOS
TNEG
RNEG
RPOS
DPM
MTIP
MRING
-
INT
SDI
SDO
CS
SCLK
CLKE
DS40F2
Share Link: 