CS8403A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CS8403A Datasheet PDF : 33 Pages
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CS8403A CS8404A
GENERAL DESCRIPTION
The CS8403A/4A are monolithic CMOS circuits
that encode and transmit audio and digital data ac-
cording to the AES/EBU, IEC958 (S/PDIF), and
EIAJ CP-340 interface standards. Both chips ac-
cept audio and control data separately, multiplex
and biphase-mark encode the data internally, and
drive it, directly or through a transformer, to a
transmission line. The CS8403A is fully software
programmable through a parallel port and contains
buffer memory for control data, while the
CS8404A has dedicated pins for the most impor-
tant control bits and a serial input port for the C, U,
and V bits.
Familiarity with the AES/EBU and IEC958 speci-
fications are assumed throughout this data sheet.
Many terms such as channel status, user data, aux-
iliary data, professional mode, etc. are not defined.
The Application Note, Overview of AES/EBU
Digital Audio Interface Data Structures, provides
an overview of the AES/EBU and IEC958 specifi-
cations and is included for clarity; however, it is not
meant to be a complete reference, and the complete
standards should be obtained from the Audio Engi-
neering Society or ANSI for the AES/EBU docu-
ment, and the International Electrotechnical
Commission for the IEC document.
Line Drivers
The RS422 line drivers for both the CS8403A and
CS8404A are low skew, low impedance, differen-
tial outputs capable of driving 110 Ω transmission
lines with a 4 Vpp signal when configured as
shown in Appendix A. To prevent possible short
circuits, both drivers are set to ground when no
master clock (MCK) is provided. They can also be
disabled by resetting the device (RST = low). Ap-
pendix A contains more information on the line
drivers. A 0.1 µF capacitor, with short leads, should
be placed as close as possible to the VD+ and GND
pins.
CS8403A DESCRIPTION
The CS8403A accepts 16- to 24-bit audio samples
through a configurable serial port, and channel sta-
tus, user, and auxiliary data through an 8-bit paral-
lel port. The parallel port allows access to 32 bytes
of internal memory which is used to store control
information and buffer channel status, user, and
auxiliary data. This data is multiplexed with the au-
dio data from the serial port, the parity bit is gener-
ated, and the bit stream is biphase-mark encoded
and driven through an RS422 line driver. A block
diagram of the CS8403A is shown in Figure 4. In
accordance with the professional definition of
channel status, the CRCC code (C.S. byte 23) can
be internally generated.
Parallel Port
The parallel port accesses one status register, three
control registers, and 28 bytes of dual port buffer
memory. The address bus and RD/WR line must be
valid when CS goes low. If RD/WR is low, the val-
ue on the data bus will be written into the buffer
memory at the specified address. If RD/WR is high,
the value in the buffer memory, at the specified ad-
dress, is placed on the data bus. The detailed timing
for reading and writing the CS8403A can be found
in the Digital Switching Characteristics table. The
memory space is allocated as shown in Figure 5.
There are three defined buffer memory modes se-
lectable by two bits in control register 2.
Status and Control Registers
Upon power up the CS8403A control registers con-
tain all zeros. Therefore, the part is initially in reset
and is muted. One's must be written to control reg-
ister 2, bits RST and MUTE, before the part will
transmit data. The remaining registers are not ini-
tialized on power-up and may contain random da-
ta.
The first register, shown in Figure 6, is the status
register in which only three bits are valid. The low-
er three bits contain flags indicating the position of
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DS239PP1
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