CYM1831 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CYM1831 Datasheet PDF : 8 Pages
| |||
CYM1831
AC Test Loads and Waveforms
R1 481 Ω
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
R1 481 Ω
5V
R2 OUTPUT
255Ω
5 pF
INCLUDING
JIG AND
SCOPE
(b)
R2
255Ω
3.0V
GND
< 5 ns
ALL INPUT PULSES
90%
10%
90%
10%
< 5 ns
Equivalent to: THÉVENIN EQUIVALENT
OUTPUT
167Ω
1.73V
Switching Characteristics Over the Operating Range[3]
1831-15 1831-20 1831-25 1831-30 1831-35 1831-45
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
tAA
tOHA
Read Cycle Time
15
20
25
30
35
45
ns
Address to Data Valid
15
20
25
30
35
45 ns
Data Hold from
3
3
3
3
3
3
ns
Address Change
tACS
CS LOW to Data Valid
15
20
25
30
35
45 ns
tDOE
OE LOW to Data Valid
8
10
15
20
20
30 ns
tLZOE
OE LOW to Low Z
0
0
0
0
0
0
ns
tHZOE
tLZCS
OE LOW to High Z
8
10
15
15
20
20 ns
CS LOW to Low Z[4]
0
3
3
3
3
ns
0
tHZCS
CS HIGH to High Z[4, 5]
6
WRITE CYCLE[6]
8
13
15
20
20 ns
tWC
Write Cycle Time
15
20
25
30
35
45
ns
tSCS
CS LOW to Write End 10
15
20
25
30
40
ns
tAW
Address Set-Up to
10
15
20
25
30
40
ns
Write End
tHA
Address Hold from
2
2
2
2
2
2
ns
Write End
tSA
Address Set-Up to
2
2
2
2
2
2
ns
Write Start
tPWE
WE Pulse Width
10
15
20
25
25
30
ns
tSD
Data Set-Up to Write 8
End
12
15
15
20
20
ns
tHD
Data Hold from Write 2
2
2
2
2
2
ns
End
tLZWE
tHZWE
WE HIGH to Low Z
3
3
3
3
3
3
ns
WE LOW to High Z[5] 0
7
0 10 0 13 0 15 0 20 0 20 ns
Note:
3. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
4. At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device. These parameters are guaranteed by design and not 100% tested.
5. tHZCS and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage.
6. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05270 Rev. **
Page 3 of 8
Share Link: 