DRPIC166X View Datasheet(PDF) - Digital Core Design
Part Name
Description
Manufacturer
DRPIC166X Datasheet PDF : 8 Pages
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DELIVERABLES
♦ Source code:
◊ VHDL Source Code or/and
◊ VERILOG Source Code or/and
◊ Encrypted, or plain text EDIF netlist
♦ VHDL & VERILOG test bench
environment
◊ Active-HDL automatic simulation macros
◊ ModelSim automatic simulation macros
◊ Tests with reference responses
♦ Technical documentation
◊ Installation notes
◊ HDL core specification
◊ Datasheet
♦ Synthesis scripts
♦ Example application
♦ Technical support
◊ IP Core implementation support
◊ 3 months maintenance
● Delivery the IP Core updates, minor
and major versions changes
● Delivery the documentation updates
● Phone & email support
CONFIGURATION
The following parameters of the DRPIC166X
core can be easy adjusted to requirements of
dedicated application and technology.
Configuration of the core can be prepared by
effortless changing appropriate constants in
package file. There is no need to change any
parts of the code.
SYMBOL
clk
clkwdt
por
mclr
prgdata(13:0)
prgaddr(15:0)
ramdatai(7:0)
int
t0cki
t1cki
ccp1i
rxdi
txcki
portai(7:0)
portbi(7:0)
portci(7:0)
portdi(7:0)
ramdatao(7:0)
rdaddr(8:0)
wraddr(8:0)
ramwe
ramoe
sleep
ccp1o
rxdo
txcko
portao(7:0)
portbo(7:0)
portco(7:0)
portdo(7:0)
trisa(7:0)
trisb(7:0)
trisc(7:0)
trisd(7:0)
docddatai
DoCDTM Interface
docddatao
docdclk
prgdatao(13:0)
prgwe
•
Number
levels
of
hardware
stack
• Memories type
• SLEEP mode
• WATCHDOG Timer
• Timer 0, 1, 2 system
• Compare Capture PWM
• USART
• PORTS A,B,C,D
• DoCDTM Debug Unit
- 1-16
- default 8
- synchronous
- asynchronous
- used
- unused
- used / width
- unused
- used
- unused
- used
- unused
- used
- unused
- used
- unused
- used
- unused
All trademarks mentioned in this document
are trademarks of their respective owners.
PINS DESCRIPTION
PIN
clk
clkwdt
por
mclr
prgdata[13:0]
ramdati[7:0]
Int
t0cki
t1cki
ccp1i
rxdti
txcki
portxi[7:0]
docddatai
TYPE
DESCRIPTION
input
input
input
input
input
input
input
input
input
input
input
input
input
input
Global clock
Watchdog clock
Global reset Power On Reset
User reset
Data bus from program memory
Data bus from int. data memory
External interrupt
Timer 0 input
Timer 1 input
Compare Capture channel input
USART serial data input
USART serial clock input
Port A, B, C, D input
DoCDTM Debugger input
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
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