DRPIC166X View Datasheet(PDF) - Digital Core Design

Part Name

Description

Manufacturer

DRPIC166X

High Performance Configurable 8-bit RISC Microcontroller

Digital Core Design 

prgaddr[15:0]

ramdatao[7:0]

rdaddr[8:0]

wraddr[8:0]

ramwe

ramoe

sleep

ccp1o

txcko

rxdto

portxo[7:0]

trisx[7:0]

docddatao

docdclk

prgdatao[13:0]

prgwe

output Program memory address bus

output Data bus for internal data memory

output RAM read address bus

output RAM write address bus

output Data memory write

output Data memory output enable

Output Sleep signal

Output Compare Capture channel output

Output USART serial clock output

Output USART serial data output

Output Port A, B, C, D outputs

Output Ports A, B, C, D data direction pins

Output DoCDTM Debugger data output

Output DoCDTM Clock line

Output Program Memory data output

Output Program Memory write enable

Indirect addressing is possible by using the

INDF register. Any instruction using INDF

register actually accesses data pointed to by

the file select register FSR. Reading INDF

register indirectly will produce 00h. Writing to

the INDF register indirectly results in a no-

operation. An effective 9-bit address is

obtained by concatenating the IRP bit

(STATUS) and the 8-bit FSR register.

clk

por

Hardware

Stack

ALU

mclr

sleep

prgdata

prgaddr

Control

Unit

RAM

Controller

ramdatai

ramdatao

rdaddr

wraddr

ramwe

ramoe

BLOCK DIAGRAM

ALU – Arithmetic Logic Unit performs

arithmetic and logic operations during

execution of an instruction. This module

contains work register (W) and Status register.

Control Unit – It performs the core

synchronization and data flow control. This

module manages execution of all instructions.

Performs decode and control functions for all

other blocks. It contains program counter (PC)

and hardware stack.

Hardware Stack – it’s a configurable

hardware stack. The stack space is not a part

of either program or data space and the stack

pointer is not readable or writable. The PC is

pushed onto the stack when CALL instruction

is executed or an interrupt causes a branch.

The stack is popped while RETURN, RETFIE

and RETLW instruction execution. The stack

operates as a circular buffer. This means that

after the stack has been pushed eight times,

the ninth push overwrites the value that was

stored from the first push.

RAM Controller – It performs interface

functions between Data memory and

DRPIC166X internal logic. It assures correct

Data Memory addressing and data transfers.

The DRPIC166X supports two addressing

modes: direct or indirect. In Direct Addressing

the 9-bit direct address is computed from

RP(1:0) bits (STATUS) and 7 least significant

bits of instruction word.

All trademarks mentioned in this document

are trademarks of their respective owners.

int

Interrupt

Controller

t0cki

Timer 0

t1cki

Timer 1

Timer 2

clkwdt

Watchdog

Timer

I/O

Ports

Compare/

Capture/

PWM

USART

DoCDTM

Debugger

portai

portbi

portci

portdi

portao

portbo

portco

portdo

trisa

trisb

trisc

trisd

ccp1i

ccp1o

rxdi

txcki

rxdo

txcko

docddatai

docddatao

docdclk

prgdatao

prgwe

Timer 0 – Main system’s timer and prescaler.

This timer operates in two modes: 8-bit timer

or 8-bit counter. In the “timer mode”, timer

registers are incremented every 4 CLK

periods. When the prescaler is assigned into

the TIMER prescale ration can be divided by

2, 4 .. 256. In the “counter mode” the timer

register is incremented every falling or rising

edge of T0CKI pin, dependent on T0SE bit in

OPTION register.

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Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

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