DRPIC166X View Datasheet(PDF) - Digital Core Design

Part Name

Description

Manufacturer

DRPIC166X

High Performance Configurable 8-bit RISC Microcontroller

Digital Core Design 

Timer 1 – Timer 1 is a 16-bit timer consisted

of two 8-bit registers (TMR1H and TMR1L).

Timer 1 can operate either as a 16 bit timer

incremented every CLK clock period or as a

Counter incremented by rising edge on the

T1CKI input pin. The Timer1 interrupt is

generated by the timer overflow.

Timer 2 – Is a 8-bit Timer with a prescaler

and postscaler. Timer2 is suitable as PWM

time-base. The Timer2 module has an 8-bit

period register, PR2. Timer2 is incremented

until it matches PR2 and then resets on the

next increment cycle. The match output of the

TMR2 register goes through a 4-bit postscaler

to generate a TMR2 interrupt.

Interrupt Controller – Interrupt Controller

module is responsible for interrupt manage

system for the external and internal interrupt

sources. It contains interrupt related registers

called INTCON, PIE1, PIR1. There are seven

individually maskable interrupt sources:

♦ Two external interrupts – INT pin,

PORTB change (pins B7:B4)

♦ Five internal interrupts – Timers 0, 1, 2,

USART, CCP1

The interrupt control register INTCON and

PIR1 records individual interrupt requests in

flag bits. A global interrupt enable bit, GIE and

Peripheral interrupts enable bit, PIE enables

all unmasked interrupts. Each interrupt source

has an individual enable bit, which can enable

or disable corresponding interrupt. When an

interrupt is responded to, the GIE is cleared to

disable any further interrupt, the return

address is pushed into the stack and the PC is

loaded with 0004h. The interrupt flag bits must

be cleared in software before re-enabling

interrupts.

I/O Ports – Block contains DRPIC166X’s

general purpose I/O ports and data direction

registers (TRIS). The DRPIC166X has four 8-

bit full bi-directional ports PORT A, PORT B,

PORT C, PORT D. Each port’s bit can be

individually accessed by bit addressable

instructions. Read and write accesses to the

I/O port are performed via their corresponding

SFR’s PORTA, PORTB, PORTC, PORTD.

The reading instruction always reads the

status of Port pins. Writing instructions always

write into the Port latches. Each port’s pin has

an corresponding bit in TRISA, B, C and D

registers. When the bit of TRIS register is set

this means that the corresponding bit of port is

All trademarks mentioned in this document

are trademarks of their respective owners.

configured as an input (output drivers are set

into the High Impedance).

CCP/PWM – The CCP module contains a 16-

bit register which can operate as a 16-bit

capture register, 16-bit compare register, or as

a PWM master/slave duty cycle register.

Watchdog Timer– it’s a free running timer.

WDT has own clock input separate from

system clock. It means that the WDT will run

even if the system clock is stopped by

execution of SLEEP instruction. During normal

operation, a WDT time-out generates a

Watchdog reset. If the device is in SLEEP

mode the WDT time-out causes the device to

wake-up and continue with normal operation.

USART – The Universal Synchronous

Asynchronous Receiver Transmitter module is

also known as a Serial Communication

Interface (SCI). The USART can be

configured as a full duplex asynchronous

system that can communicate with peripheral

devices or it can be configured as a half

duplex synchronous system (Master or Slave).

DoCD™ Debug Unit – it’s a real-time

hardware debugger provides debugging

capability of a whole SoC system. In contrast

to other on-chip debuggers DoCD™ provides

non-intrusive debugging of running

application. It can halt, run, step into or skip

an instruction, read/write any contents of

microcontroller including all registers, internal,

external, program memories, all SFRs

including user defined peripherals. Hardware

breakpoints can be set and controlled on

program memory, internal and external data

memories, as well as on SFRs. Hardware

breakpoint is executed if any write/read

occurred at particular address with certain

data pattern or without pattern. The DoCD™

system includes three-wire interface and

complete set of tools to communicate and

work with core in real time debugging. It is

built as scalable unit and some features can

be turned off to save silicon and reduce power

consumption. A special care on power

consumption has been taken, and when

debugger is not used it is automatically

switched in power save mode. Finally whole

debugger is turned off when debug option is

no longer used.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

Share Link: