DRPIC166X View Datasheet(PDF) - Digital Core Design

Part Name

Description

Manufacturer

DRPIC166X

High Performance Configurable 8-bit RISC Microcontroller

Digital Core Design 

OPTIONAL

PERIPHERALS

There are also available an optional

peripherals, not included in presented

DRPIC166X Microcontroller Core. The

optional peripherals, can be implemented in

microcontroller core upon customer request.

● SPI – Master and Slave Serial Peripheral

Interface

○ Supports speeds up ¼ of system clock

○ Mode fault error

○ Write collision error

○ Software selectable polarity and phase of

serial clock SCK

○ System errors detection

○ Allows operation from a wide range of system

clock frequencies (build-in 5-bit timer)

○ Interrupt generation

● I2C bus controller - Master

○ 7-bit and 10-bit addressing modes

○ NORMAL, FAST, HIGH speeds

○ Multi-master systems supported

○ Clock arbitration and synchronization

○ User defined timings on I2C lines

○ Wide range of system clock frequencies

○ Interrupt generation

● I2C bus controller - Slave

○ NORMAL speed 100 kbs

○ FAST speed 400 kbs

○ HIGH speed 3400 kbs

○ Wide range of system clock frequencies

○ User defined data setup time on I2C lines

○ Interrupt generation

PERFORMANCE

The following table gives a survey about

the Core area and performance in the

ALTERA® devices after Place & Route:

Device

Speed

grade

Logic Cells

Fmax

CYCLONE

-6

1654

81 MHz

CYCLONE II -6

1654

72 MHz

STRATIX

-5

1655

86 MHz

STRATIX II

-3

1401

166 MHz

STRATIX GX -5

1655

84 MHz

APEX II

-7

1695

74 MHz

APEX20KC

-7

1695

64 MHz

APEX20KE

-1

1695

54 MHz

APEX20K

-1

1695

50 MHz

ACEX1K

-1

1695

52 MHz

FLEX10KE

-1

1695

54 MHz

Core performance in ALTERA® devices

Area utilized by the each unit of DRPIC166X

core in vendor specific technologies is

summarized in table below.

Component

Area

[LC]

[FFs]

CPU*

904

296

Timer 0

60

29

Timer 1

81

30

Timer 2

90

34

USART

257

100

CCP1

111

32

Watchdog Timer

55

38

I/O Ports

96

64

Total area

1 654

625

*CPU – consisted of ALU, Control Unit, Bus Controller, Hardware Stack,

External INT pin Interrupt Controller, Extended interrupt controller,(512

Bytes RAM and 8kW of program memory)

Core components area utilization

All trademarks mentioned in this document

are trademarks of their respective owners.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

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