DS1338Z-18 View Datasheet(PDF) - Maxim Integrated

Part Name

Description

Manufacturer

DS1338Z-18

I2C RTC with 56-Byte NV RAM

Maxim Integrated 

POWER-UP/POWER-DOWN CHARACTERISTICS

(TA = -40°C to +85°C) (Note 1, Figure 1)

PARAMETER

SYMBOL

Recovery at Power-Up (Note 15)

tREC

VCC Fall Time; VPF(MAX) to VPF(MIN)

tVCCF

VCC Rise Time; VPF(MIN) to VPF(MAX)

tVCCR

DS1338 I2C RTC with 56-Byte NV RAM

MIN

TYP

MAX UNITS

2

ms

300

s

0

s

Warning: Negative undershoots below -0.3V while the part is in battery-backed mode may cause

loss of data.

Note 1:

Note 2:

Note 3:

Note 4:

Note 5:

Note 6:

Note 7:

Note 8:

Note 9:

Note 10:

Note 11:

Note 12:

Note 13:

Note 14:

Note 15:

Limits at -40°C are guaranteed by design and not production tested.

All voltages are referenced to ground.

SCL only.

SDA and SQW/OUT.

ICCA—SCL clocking at max frequency = 400kHz.

Specified with the I2C bus inactive.

Measured with a 32.768kHz crystal attached to X1 and X2.

After this period, the first clock pulse is generated.

A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to

bridge the undefined region of the falling edge of SCL.

The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL signal.

A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ to 250ns must then be met. This is

automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW

period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns before the SCL line

is released.

CB—total capacitance of one bus line in pF.

Guaranteed by design. Not production tested.

The parameter tOSF is the time period the oscillator must be stopped for the OSF flag to be set over the voltage range of

0.0V ≤ VCC ≤ VCC(MAX) and 1.3V ≤ VBAT ≤ 3.7V.

This delay applies only if the oscillator is enabled and running. If the oscillator is disabled or stopped, no power-up delay occurs.

Figure 1. Power-Up/Power-Down Timing

VPF(MVACXC)

VPF(MIN)

t VCCF

INPUTS

RECOGNIZED

DON'T CARE

t VCCR

tREC

RECOGNIZED

OUTPUTS

VALID

HIGH-Z

VALID

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