DS2408 View Datasheet(PDF) - Maxim Integrated

Part Name

Description

Manufacturer

DS2408

1-Wire 8-Channel Addressable Switch

Maxim Integrated 

DS2408

Control/Status Register

The data in this register reports status information, determines the function of the RSTZ pin and further

configures the device for conditional search. This register can only be written through the Write Condi-

tional Search Registers command.

Control/Status Register Bitmap

ADDR b7

b6

b5

b4

b3

b2

b1

b0

008Dh VCCP

0

0

0

PORL ROS

CT

PLS

This register is read/write. Without VCC supply, this register reads 08h after a power-on reset. The func-

tional assignments of the individual bits are explained in the table below. Bits 4 to 6 have no function;

they will always read 0 and cannot be set to 1.

Control/Status Register Details

BIT DESCRIPTION

PLS: Pin or Activity

Latch Select

CT: Conditional Search

Logical Term

ROS: RSTZ Pin Mode

Control

PORL: Power-On Reset

Latch

VCCP: VCC Power

Status (Read-Only)

BIT(S)

b0

b1

b2

b3

b7

DEFINITION

Selects either the PIO pins or the PIO activity latches as input for the

conditional search.

0: pin selected (default)

1: activity latch selected

Specifies whether the data of two or more channels needs to be OR’ed

or AND’ed to meet the qualifying condition for the device to respond to a

conditional search. If only a single channel is selected in the channel

selection mask (008Bh) this bit is a don't care.

0: bitwise OR (default)

1: bitwise AND

Configures RSTZ as either RST input or STRB output

0: configured as RST input (default)

1: configured as STRB output

Specifies whether the device has performed a power-on reset. This bit

can only be cleared to 0 under software control. As long as this bit is 1

the device will always respond to a conditional search.

For VCC powered operation the VCC pin needs to be tied to a voltage

source ³ VPUP.

0: VCC pin is grounded

1: VCC -powered operation

The interaction of the various signals that determine whether the device responds to a conditional search

is illustrated in Figure 7. The selection mask SM selects the participating channels. The polarity selection

SP determines for each channel whether the channel signal needs to be 1 or 0 to qualify. The PLS bit

determines whether all channel signals are taken from the activity latches or I/O pins. The signals of all

channels are fed into an AND gate as well as an OR gate. The CT bit finally selects the AND’ed or

OR’ed result as the conditional search response signal CSR.

Note on CT bit:

OR The qualifying condition is met if the input (pin state or activity latch) for one or more selected

channels matches the corresponding polarity.

AND For the qualifying condition to be met, the input (pin state or activity latch) for every selected

channel must match the corresponding polarity.

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