DSP56001 View Datasheet(PDF) - Motorola => Freescale

Part Name

Description

Manufacturer

DSP56001

24-Bit General Purpose Digital Signal Processor

Motorola => Freescale 

External Clock/Crystal Input (EXTAL)

EXTAL may be used to interface the crystal oscillator input to an exter-

nal crystal or an external clock.

Crystal Output (XTAL)

This output connects the internal crystal oscillator output to an external

crystal. If an external clock is used, XTAL should not be connected.

HOST INTERFACE

Host Data Bus (H0-H7)

This bidirectional data bus is used to transfer data between the host

processor and the DSP56001. This bus is an input unless enabled by

a host processor read. H0-H7 may be programmed as general pur-

pose parallel I/O pins called PB0-PB7 when the Host Interface is not

being used. These pins are configured as a GPIO input pins during

hardware reset.

Host Address (HA0-HA2)

These inputs provide the address selection for each Host Interface

register. HA0-HA2 may be programmed as general purpose parallel

I/O pins called PB8-PB10 when the Host Interface is not being used.

These pins are configured as a GPIO input pins during hardware reset.

Host Read/Write (HR/W)

This input selects the direction of data transfer for each host processor

access. HR/W may be programmed as a general purpose I/O pin

called PB11 when the Host Interface is not being used. This pin is con-

figured as a GPIO input pins during hardware reset.

Host Enable (HEN)

This input enables a data transfer on the host data bus. When HEN is

asserted and HR/W is high, H0-H7 become outputs, and DSP56001

data may be read by the host processor, When HEN is asserted and

HR/W is low, H0-H7 become inputs and host data is latched inside the

DSP when HEN is deasserted. Normally a chip select signal, derived

from host address decoding and an enable clock, is used to generate

HEN. HEN may be programmed as a general purpose I/O pin called

PB12 when the Host Interface is not being used. This pin is configured

as a GPIO input pins during hardware reset.

Host Request (HREQ)

This open-drain output signal is used by the DSP56001 Host Interface

to request service from the host processor, DMA controller, or simple

external controller. HREQ may be programmed as a general purpose

I/O pin (not open-drain) called PB13 when the Host interface is not be-

ing used. HREQ should be pulled high when not in use. This pin is con-

figured as a GPIO input pins during hardware reset.

Host Acknowledge (HACK)

This input has two functions: 1) to receive a Host Acknowledge hand-

shake signal for DMA transfers and, 2) to receive a Host Interrupt Ac-

knowledge compatible with MC68000 Family processors. HACK may

be programmed as a general purpose I/O pin called PB14 when the

Host Interface is not being used. This pin is configured as a GPIO input

pins during hardware reset. HACK should be pulled high when not

in use.

Transmit Data (TXD)

This output transmits serial data from the SCI Transmit Shift Register.

Data changes on the negative edge of the transmit clock. This output

is stable on the positive edge of the transmit clock. TXD may be pro-

grammed as a general purpose I/O pin called PC1 when the SCI is not

being used. This pin is configured as a GPIO input pins during hard-

ware reset.

SCI Serial Clock (SCLK)

This bidirectional pin provides an input or output clock from which the

transmit and/or receive baud rate is derived in the asynchronous mode

and from which data is transferred in the synchronous mode. SCLK

may be programmed as a general purpose I/O pin called PC2 when

the SCI is not being used. This pin is configured as a GPIO input pins

during hardware reset.

SYNCHRONOUS SERIAL INTERFACE (SSI)

Serial Control Zero (SC0)

This bidirectional pin is used for control by the SSI. SC0 may be pro-

grammed as a general purpose I/O pin called PC3 when the SSI is not

being used. This pin is configured as a GPIO input pins during hard-

ware reset.

Serial Control One (SC1)

This bidirectional pin is used for control by the SSI. SC1 may be pro-

grammed as a general purpose I/O pin called PC4 when the SSI is not

being used. This pin is configured as a GPIO input pins during hard-

ware reset.

Serial Control Two (SC2)

This bidirectional pin is used for control by the SSI. SC2 may be pro-

grammed as a general purpose I/O pin called PC5 when the SSI is not

being used. This pin is configured as a GPIO input pins during hard-

ware reset.

SSI Serial Clock (SCK)

This bidirectional pin provides the serial bit rate clock for the SSI when

only one clock is used. SCK may be programmed as a general pur-

pose I/O pin called PC6 when the SSI is not being used. This pin is

configured as a GPIO input pins during hardware reset.

SSI Receive Data (SRD)

This input pin receives serial data into the SSI Receive Shift Register.

SRD may be programmed as a general purpose I/O pin called PC7

when the SSI is not being used. This pin is configured as a GPIO input

pins during hardware reset.

SSI Transmit Data (STD)

This output pin transmits serial data from the SSI Transmit Shift Reg-

ister. STD may be programmed as a general purpose I/O pin called

PC8 when the SSI is not being used. This pin is configured as a GPIO

input pins during hardware reset.

SERIAL COMMUNICATIONS INTERFACE (SCI)

Receive Data (RXD)

This input receives byte-oriented data into the SCI Receive Shift Reg-

ister. Input data is sampled on the positive edge of the Receive Clock.

RXD may be programmed as a general purpose I/O pin called PC0

when the SCI is not being used. This pin is configured as a GPIO input

pins during hardware reset.

MOTOROLA

4

DSP56001

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