EN25Q80A-100G View Datasheet(PDF) - Eon Silicon Solution Inc.

Part Name

Description

Manufacturer

EN25Q80A-100G

8 Megabit Serial Flash Memory

Eon Silicon Solution Inc. 

EN25Q80A

Figure 9. Write Status Register Instruction Sequence Diagram

Figure 9.1 Write Status Register Instruction Sequence under EQIO Mode

Read Data Bytes (READ) (03h)

The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read Data

Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the

rising edge of Serial Clock (CLK). Then the memory contents, at that address, is shifted out on Serial

Data Output (DO), each bit being shifted out, at a maximum frequency fR, during the falling edge of

Serial Clock (CLK).

The instruction sequence is shown in Figure 10. The first byte addressed can be at any location. The

address is automatically incremented to the next higher address after each byte of data is shifted out.

The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When

the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence

to be continued indefinitely.

This Data Sheet may be revised by subsequent versions

17

or modifications due to changes in technical specifications.

©2004 Eon Silicon Solution, Inc.,

Rev. D, Issue Date: 2009/10/13

www.eonssi.com

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