FDC37N869 View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

Manufacturer

FDC37N869

5V and 3.3V Super I/O Controller with Infrared Support for Portable Applications

SMSC -> Microchip 

PIN DESCRIPTION

BUFFER TYPE PER PIN

TQFP

PIN #

46-49

51-54

42

43

44

26-32

39-41,

95,35,

36,1,

3,25

19,50,

97,17

20,34,

94,22

33

37

38

55

98

14

NAME

Data Bus 0-

7

nI/O Read

nI/O Write

Address

Enable

Address

Bus

DMA

Request

A, B, C, D

nDMA

Acknowl-

edge

A, B, C, D

Terminal

Count

Serial IRQ

PCI Clock

Reset

I/O Channel

Ready

(Note 4)

nRead Disk

Data

Table 1 - DESCRIPTION OF PIN FUNCTIONS

SYMBOL

BUFFER

MODE6

DESCRIPTION

HOST PROCESSOR INTERFACE

D0-D7

IO12

The data bus connection used by the host

microprocessor to transmit data to and from the

chip. These pins are in a high-impedance state

when not in the output mode.

nIOR

IS

This active low signal is issued by the host

microprocessor to indicate an I/O read

operation.

nIOW

IS

This active low signal is issued by the host

microprocessor to indicate an I/O write

operation.

AEN

IS

Active high Address Enable indicates DMA

operations on the host data bus. Used internally

to qualify appropriate address decodes.

A0-A15

I

These host address bits determine the I/O

address to be accessed during nIOR and nIOW

cycles. These bits are latched internally by the

leading edge of nIOR and nIOW. All internal

address decodes use the full A0 to A15 address

bits.

DRQ_A

O12

These active high outputs are the DMA request

DRQ_B

for byte transfers of data between the host and

DRQ_C

the chip. These signals are cleared on the last

DRQ_D

byte of the data transfer by the nDACK signal

going low (or by nIOR going low if nDACK was

already low as in demand mode).

nDACK_A

IS

These are active low inputs acknowledging the

nDACK_B

request for a DMA transfer of data between the

nDACK_C

host and the chip. These inputs enable the DMA

nDACK_D

read or write internally.

TC

IS

This signal indicates that DMA data transfer is

complete. TC is only accepted when nDACK_x

is low. In AT and PS/2 model 30 modes, TC is

active high and in PS/2 mode, TC is active low.

SIRQ

IO12

Serial IRQ pin used with the CLK33 pin to

transfer FDC37N869 interrupts to the host.

CLK33

ICLK

33MHz PCI clock input, used with the SIRQ and

the nCLKRUN pins to serially transfer

FDC37N869 interrupts to the host.

RESET_

IS

This active high signal resets the chip and must

DRV

be valid for 500ns minimum. The effect on the

internal registers is described in the appropriate

section. The configuration registers are not

affected by this reset.

IOCHRDY

OD12 This pin is pulled low to extend the read/write

command. IOCHRDY can used by the IRCC and

by the Parallel Port in EPP mode.

FLOPPY DISK INTERFACE

nRDATA

IS

Raw serial bit stream from the disk drive, low

active. Each falling edge represents a flux

transition of the encoded data.

SMSC DS – FDC37N869

Page 9

Rev. 11/09/2000

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