FS6370 View Datasheet(PDF) - Unspecified
Part Name
Description
Manufacturer
FS6370 Datasheet PDF : 25 Pages
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FS6370-01
EEPROM Programmable 3-PLL Clock Generator IC
9.0 Programming Information
Table 3: Register Map (Note: All Register Bits are cleared to zero on power-up.)
ADDRESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BYTE 15
MUX_D2[1:0]
(selected via SEL_CD = 1)
MUX_C2[1:0]
(selected via SEL_CD = 1)
PDPOST_D PDPOST_C PDPOST_B PDPOST_A
BYTE 14
POST_D2[3:0]
(selected via SEL_CD = 1)
POST_C2[3:0]
(selected via SEL_CD = 1)
BYTE 13
POST_D1[3:0]
(selected via SEL_CD = 0)
POST_C1[3:0]
(selected via SEL_CD = 0)
BYTE 12
POST_B[3:0]
POST_A[3:0]
BYTE 11
MUX_D1[1:0]
(selected via SEL_CD = 0)
Reserved (0)
LFTC_C2
(SEL_CD=1)
CP_C2
(SEL_CD=1)
FBKDIV_C2[10:8] M-Counter
(selected via SEL_CD pin = 1)
BYTE 10
FBKDIV_C2[7:3] M-Counter
(selected via SEL_CD pin = 1)
FBKDIV_C2[2:0] A-Counter
(selected via SEL_CD pin = 1)
BYTE 9
REFDIV_C2[7:0]
(selected via SEL_CD pin = 1)
BYTE 8
MUX_C1[1:0]
(selected via SEL_CD = 0)
PDPLL_C
LFTC_C1
CP_C1
(SEL_CD=0) (SEL_CD=0)
FBKDIV_C1[10:8] M-Counter
(selected via SEL_CD = 0)
BYTE 7
FBKDIV_C1[7:3] M-Counter
(selected via SEL_CD = 0)
FBKDIV_C1[2:0] A-Counter
(selected via SEL_CD = 1)
BYTE 6
REFDIV_C1[7:0]
(selected via SEL_CD = 0)
BYTE 5
MUX_B[1:0]
PDPLL_B
LFTC_B
CP_B
FBKDIV_B[10:8] M-Counter
BYTE 4
FBKDIV_B[7:3] M-Counter
FBKDIV_B[2:0] A-Counter
BYTE 3
REFDIV_B[7:0]
BYTE 2
MUX_A[1:0]
PDPLL_A
LFTC_A
CP_A
FBKDIV_A[10:8] M-Counter
BYTE 1
FBKDIV_A[7:3] M-Counter
FBKDIV_A[2:0] A-Counter
BYTE 0
9.1 Control Bit Assignments
REFDIV_A[7:0]
If the power-down bit contains a zero, the related circuit
will continue to function regardless of the PD pin state.
If any PLL control bit is altered during device operation,
including those bits controlling the Reference and Feed-
back Dividers, the output frequency will slew smoothly (in
a glitch-free manner) to the new frequency. The slew rate
is related to the programmed loop filter time constant.
However, any programming changes to any Mux or Post
Divider control bits will cause a glitch on an operating
clock output.
9.1.1 Power Down
All power-down functions are controlled by enable bits.
That is, the bits select which portions of the FS6370 to
power-down when the PD input is asserted. If the power-
down bit contains a one, the related circuit will shut down
if the PD pin is high (Run Mode only). When the PD pin is
low, power is enabled to all circuits.
Table 4: Power-Down Bits
NAME
PDPLL_A
(Bit 21)
PDPLL_B
(Bit 45)
PDPLL_C
(Bit 69)
Reserved (0)
(Bit 69)
DESCRIPTION
Power-Down PLL A
Bit = 0
Power On
Bit = 1
Power Off
Power-Down PLL B
Bit = 0
Power On
Bit = 1
Power Off
Power-Down PLL C
Bit = 0
Power On
Bit = 1
Power Off
Set these reserved bits to zero (0)
10
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