FS6370 View Datasheet(PDF) - Unspecified
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FS6370 Datasheet PDF : 25 Pages
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FS6370-01
EEPROM Programmable 3-PLL Clock Generator IC
The PFD will drive the VCO up or down in frequency until
the divided reference frequency and the divided VCO Figure 4: Feedback Divider
frequency appearing at the inputs of the PFD are equal.
The input/output relationship between the reference fre-
quency and the VCO frequency is
fVCO
Dual
Modulus
Prescaler
M
Counter
fPD
fVCO
=
f
REF
ççèæ
N
N
F
R
÷÷øö .
FBKDIV[2:0]
FBKDIV[10:3]
3.1.1 Reference Divider
The Reference Divider is designed for low phase jitter.
The divider accepts the output of the reference oscillator
and provides a divided-down frequency to the PFD. The
Reference Divider is an 8-bit divider, and can be pro-
grammed for any modulus from 1 to 255 by programming
the equivalent binary value. A divide-by-256 can also be
achieved by programming the eight bits to 00h.
3.1.2 Feedback Divider
The Feedback Divider is based on a dual-modulus
prescaler technique. The technique allows the same
granularity as a fully programmable feedback divider,
while still allowing the programmable portion to operate at
low speed. A high-speed pre-divider (also called a
prescaler) is placed between the VCO and the program-
mable Feedback Divider because of the high speeds at
which the VCO can operate. The dual-modulus technique
insures reliable operation at any speed that the VCO can
achieve and reduces the overall power consumption of
the divider.
For example, a fixed divide-by-eight prescaler could have
been used in the Feedback Divider. Unfortunately, a di-
vide-by-eight would limit the effective modulus of the en-
tire feedback divider to multiples of eight. This limitation
would restrict the ability of the PLL to achieve a desired
input-frequency-to-output-frequency ratio without making
both the Reference and Feedback Divider values com-
paratively large. Generally, very large values are unde-
sirable as they degrade the bandwidth of the PLL, in-
creasing phase jitter and acquisition time.
To understand the operation of the feedback divider, refer
to Figure 4. The M-counter (with a modulus always equal
to M) is cascaded with the dual-modulus prescaler. The
A-counter controls the modulus of the prescaler. If the
value programmed into the A-counter is A, the prescaler
will be set to divide by N+1 for A prescaler outputs.
Thereafter, the prescaler divides by N until the M-counter
output resets the A-counter, and the cycle begins again.
Note that N=8, and A and M are binary numbers.
A
Counter
Suppose that the A-counter is programmed to zero. The
modulus of the prescaler will always be fixed at N; and
the entire modulus of the feedback divider becomes M×N.
Next, suppose that the A-counter is programmed to a
one. This causes the prescaler to switch to a divide-by-
N+1 for its first divide cycle and then revert to a divide-by-
N. In effect, the A-counter absorbs (or “swallows”) one
extra clock during the entire cycle of the Feedback Di-
vider. The overall modulus is now seen to be equal to
M×N+1.
This example can be extended to show that the Feed-
back Divider modulus is equal to M×N+A, where A≤M.
3.1.3 Feedback Divider Programming
For proper operation of the Feedback Divider, the A-
counter must be programmed only for values that are
less than or equal to the M-counter. Therefore, not all
divider moduli below 56 are available for use. This is
shown in Table 2.
Above a modulus of 56, the Feedback Divider can be
programmed to any value up to 2047.
Table 2: Feedback Divider Modulus Under 56
M-COUNTER:
A-COUNTER: FBKDIV[2:0]
FBKDIV[10:3] 000 001 010 011 100 101 110 111
00000001
00000010
00000011
00000100
00000101
00000110
00000111
8
9
-
-
-
-
-
-
16 17 18 -
-
-
-
-
24 25 26 27 -
-
-
-
32 33 34 35 36 -
-
-
40 41 42 43 44 45 -
-
48 49 50 51 52 53 54 -
56 57 58 59 60 61 62 63
FEEDBACK DIVIDER MODULUS
3
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