FS6377-01G View Datasheet(PDF) - AMI Semiconductor
Part Name
Description
Manufacturer
FS6377-01G Datasheet PDF : 21 Pages
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FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
Data Sheet
Table 4. Power-Down Bits
Name
PDPLL_A
(Bit 21)
PDPLL_B
(Bit 45)
PDPLL_C
(Bit 69)
Reserved (0)
(Bit 69)
PDPOSTA
(Bit 120)
PDPOSTB
(Bit 121)
PDPOSTC
(Bit 122)
PDPOSTD
(Bit 123)
Description
Power-Down PLL A
Bit = 0
Power on
Bit = 1
Power off
Power-Down PLL B
Bit = 0
Power on
Bit = 1
Power off
Power-Down PLL C
Bit = 0
Power on
Bit = 1
Power off
Set these reserved bits to zero (0)
Power-Down POST divider A
Bit = 0
Power on
Bit = 1
Power off
Power-Down POST divider B
Bit = 0
Power on
Bit = 1
Power off
Power-Down POST divider C
Bit = 0
Power on
Bit = 1
Power off
Power-Down POST divider D
Bit = 0
Power on
Bit = 1
Power off
Table 6. Divider Control Bits
Name
POST_A[3:0]
(Bits 99-96)
POST_B[3:0]
(Bits 103-100)
POST_C1[3:0]
(Bits 107-104)
POST_C2[3:0]
(Bits 115-112)
POST_D1[3:0]
(Bits 111-108)
POST_D2[3:0]
(Bits 119-116)
Description
POST divider A (see Table 7)
POST divider B (see Table 7)
POST divider C1 (see Table 7)
selected when the SEL_CD pin = 0
POST divider C2 (see Table 7)
selected when the SEL_CD pin = 1
POST divider D1 (see Table 7)
selected when the SEL_CD pin = 0
POST divider D2 (see Table 7)
selected when the SEL_CD pin = 1
Table 5. Divider Control Bits
Name
REFDIV_A[7:0]
(Bits 7-0)
REFDIV_B[7:0]
(Bits 31-24)
REFDIV_C1[7:0]
(Bits 55-48)
REFDIV_C2[7:0]
(Bits 79-72)
Description
Reference Divider A (NR)
Reference Divider B (NR)
Reference Divider C1 (NR)
selected when the SEL-CD pin = 0
Reference Divider C2 (NR)
selected when the SEL-CD pin = 1
Feedback Divider A (NF)
FBKDIV_A[10:0]
(Bits 18-8)
FBKDIV_A[2:0]
A-Counter value
FBKDIV_A[10:3] M-Counter value
Feedback Divider B (NF)
FBKDIV_B[10:0]
(Bits 42-32)
FBKDIV_C1[10:0]
(Bits 66-56)
FBKDIV_C2[10:0]
(Bits 90-80)
FBKDIV_B[2:0]
A-Counter value
FBKDIV_B[10:3] M-Counter value
Feedback Divider C1 (NF)
selected when the SEL-CD pin = 0
FBKDIV_C1[2:0] A-Counter value
FBKDIV_C1[10:3] M-Counter value
Feedback DividerC2 (NF)
selected when the SEL-CD pin = 1
FBKDIV_C2[2:0] A-Counter value
FBKDIV_C2[10:3] M-Counter value
Table 7. Post Divider Modulus
BIT [3]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
BIT [2]
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
BIT [1]
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
BIT [0]
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DIVIDE BY
1
2
3
4
5
6
8
9
10
12
15
16
18
20
25
50
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