HDMP-0452 View Datasheet(PDF) - HP => Agilent Technologies

Part Name

Description

Manufacturer

HDMP-0452

Quad Port Bypass Circuit with CDR for Fibre Channel Arbitrated Loops

HP => Agilent Technologies 

Figure 5. Eye diagram of FM_NODE[1]± high-speed differential output.

Note: Measurement taken with a 27-1 PRBS input to FM_NODE[0]±.

HP70841B

PATTERN

GENERATOR ± DATA

K28.7

CLOCK

RANDOM JITTER

2

BIAS TEE

HDMP-0452

± FM_NODE[0]

BYPASS[0]–

BYPASS[1:4]–

REFCLK

± TO_NODE[0]

1062.5 MHz

HP70311A

CLOCK SOURCE

1.4 V

2

106.25 MHz

1/10

CH 1/2

106.25 MHz

TRIGGER

HP83480A

DIGITAL

COMMUNICATION

ANALYZER

Figure 6. Setup for measurement of random jitter.

N/C

1 kΩ

HP70841B

PATTERN

GENERATOR ± DATA

+K28.5 –K28.5 CLOCK

DETERMINISTIC JITTER

2

BIAS TEE

HDMP-0452

± FM_NODE[0]

BYPASS[0]–

BYPASS[1:4]–

REFCLK

± TO_NODE[0]

1062.5 MHz

HP70311A

1/10

CLOCK SOURCE

1.4 V

106.25 MHz

2

CH 1/2

1/2

TRIGGER

106.25 MHz

53.125 MHz

HP83480A

DIGITAL

COMMUNICATION

ANALYZER

Figure 7. Setup for measurement of deterministic jitter.

N/C

1 kΩ

9

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