HMS30C7202N View Datasheet(PDF) - MagnaChip Semiconductor

Part Name

Description

Manufacturer

HMS30C7202N

Highly-intergrated MPU

MagnaChip Semiconductor 

HMS30C7202N

Figure 5-4 PMU An Externally Generated Warm Reset

nRESET is driven to `0' by external hardware. The nRESET input is filtered by a de-bounce circuit. Note that

this means that nRESET must remain low for a minimum of 40ms. BnRES (the on-chip reset signal) becomes

active as soon as nRESET is low, and high once the de-bounced nRESET goes high once more. BnRES

disables PLL1 and PLL2. The CPU may read the RESET register, which will return 0x106:

Bit

Meaning

Bit 1 set:

PLL1 has been `unlocked'

Bit 2 set:

PLL2 has been `unlocked'

Bit 8 set:

A RESET event has occurred.

Table 5-4 PMU Bit Settings for a Warm Reset within PMUSTAT Register

Note

The internal chip reset, BnRES, remains active for 20ms after an externally generated nRESET. External

devices should not assume that the HMS30C7202 is in an active state during this period.

© 2004 MagnaChip Semiconductor Ltd. All Ri3g6hts Reserved.

- 36 -

Version 1.1

Share Link: