M25P05-VMN6T View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M25P05-VMN6T

512 Kbit, Low Voltage, Serial Flash Memory With 20 MHz SPI Bus Interface

STMicroelectronics 

Figure 13. Page Program (PP) Sequence

M25P05

S

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39

C

Instruction

24-Bit Address

Data Byte 1

D

23 22 21 3 2 1 0 7 6 5 4 3 2 1 0

MSB

MSB

S

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

C

Data Byte 2

Data Byte 3

Data Byte 128

D

7654321076543210

76543210

MSB

MSB

MSB

AI03749C

Note: 1. Address bits A23 to A16 must be set to 00h.

Page Program (PP)

The Page Program (PP) instruction allows bytes to

be programmed in the memory (changing bits from

1 to 0). Before it can be accepted, a Write Enable

(WREN) instruction must previously have been ex-

ecuted. After the Write Enable (WREN) instruction

has been decoded, the device sets the Write En-

able Latch (WEL).

The Page Program (PP) instruction is entered by

driving Chip Select (S) Low, followed by the in-

struction code, three address bytes (of which the

most significant byte, A23-A16, must be 00h) and

at least one data byte on Serial Data Input (D). If

the 7 least significant address bits (A6-A0) are not

all zero, all transmitted data exceeding the ad-

dressed page boundary roll over, and are pro-

grammed from the start address of the same page

(the one whose 7 least significant address bits

(A6-A0) are all zero). Chip Select (S) must be driv-

en Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 13.

If more than 128 bytes are sent to the device, pre-

viously latched data are discarded and the last 128

data bytes are guaranteed to be programmed cor-

rectly within the same page. If less than 128 Data

bytes are sent to device, they are correctly pro-

grammed at the requested addresses without hav-

ing any effects on the other bytes of the same

page.

Chip Select (S) must be driven High after the

eighth bit of the last data byte has been latched in,

otherwise the Page Program (PP) instruction is not

executed.

As soon as Chip Select (S) is driven High, the self-

timed Page Program cycle (whose duration is tPP)

is initiated. While the Page Program cycle is in

progress, the Status Register may be read to

check the value of the Write In Progress (WIP) bit.

The Write In Progress (WIP) bit is 1 during the self-

timed Page Program cycle, and is 0 when it is

completed. When the cycle is completed, the Write

Enable Latch (WEL) bit is reset.

A Page Program (PP) instruction applied to a page

which is protected by the Block Protect (BP0, BP1)

bits (see Table 2) is not executed.

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