MAX3645(2003) View Datasheet(PDF) - Maxim Integrated

Part Name

Description

Manufacturer

MAX3645
(Rev.:2003)

+2.97V to +5.5V, 125Mbps to 200Mbps Limiting Amplifier with Loss-of-Signal Detector

Maxim Integrated 

+2.97V to +5.5V, 125Mbps to 200Mbps Limiting

Amplifier with Loss-of-Signal Detector

TH CSD

POWER

DETECTOR

DIN+

DIN-

OFFSET

CORRECTION

CINT

MAX3645

LOS

LOS

DOUT+

DOUT-

DIS

VCC

VCC

VCC - 0.87V

4.8kΩ

4.8kΩ

DIN+

DIN-

ESD

STRUCTURES

CAZ1

CAZ2

Figure 2. Functional Diagram

The external autozero capacitor (CAZ), in parallel with

internal capacitance (CINT), determines the time con-

stant of the DC offset correction loop. With CAZ = 0.1µF

(recommended), the -3dB frequency cutoff of the signal

path is typically 0.5kHz.

Power Detector and LOS Indicators

The external resistor RTH sets the gain of the first limit-

ing stage. This gain setting controls the threshold at

which the power detector indicates an LOS condition.

Power detection is accomplished by rectifying and low-

pass filtering the data signal, then comparing it to the

programmed threshold voltage. A hysteresis of 2dB

prevents the LOS output from chattering when the input

signal is near the threshold.

PECL Output Buffer

The data outputs (DOUT+, DOUT-) and the loss-of-sig-

nal outputs (LOS+, LOS-) are PECL outputs. The equiv-

alent PECL output circuit is shown in Figure 4.

Applications Information

Programming LOS Assert/Deassert Levels

The appropriate value of RTH is determined by using

the Loss-Of-Signal Threshold vs. RTH graph in the

Typical Operating Characteristics.

LOS Time Constant

The lowpass filter of the power detector comprises a

20kΩ on-chip resistor (RSD) and an external capacitor

(CSD). The CSD capacitor value determines the power-

Figure 3. Equivalent Data Input Circuit

detector time constant, which determines the LOS

assert/deassert time. With CSD = 1nF the assert/

deassert time is in the range of 2.3µs to 80µs. This pro-

vides a long enough time constant to avoid false trig-

gering due to variations in mark density.

Disable Function

When the DIS input is forced high, the disable function

is enabled, which holds DOUT+ low and DOUT- high.

The disable function is used to prevent the data outputs

from toggling due to noise when no signal is present.

The LOS output can be connected to the DIS input for

automatic squelch.

PECL Output Terminations

The proper termination for a PECL output is 50Ω to

(VCC - 2V), but other standard termination techniques

can be used. For more information on PECL termina-

tions and how to interface with other logic families, refer

to Maxim Application Note HFAN-01.0: Introduction to

LVDS, PECL, and CML.

Layout Considerations

For best performance, use good high-frequency layout

techniques. Filter power supplies, keep ground con-

nections short, and use multiple vias where possible.

Power-supply decoupling should be placed close to

the VCC pins. Minimize the distance from the preampli-

fier and use controlled-impedance transmission lines to

interface with the outputs when possible.

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